3D Integration of 2D Field-Effect Transistors

Researchers from Penn State have demonstrated a novel method of 3D integration using 2D materials. This advancement, detailed in their recent study, addresses the growing challenge of fitting more transistors into increasingly smaller areas, a key concern in the semiconductor industry as devices continue to shrink in size while requiring enhanced functionality

Penn State researchers demonstrated 3D integration of semiconductors at a massive scale, characterizing tens of thousands of devices using 2D transistors made with 2D semiconductors, enabling electronic gadgets to possibly become smarter and more versatile. Image Credit: Elizabeth Flores-Gomez Murray/Materials Research Institute


The number of transistors on a chip will double every two years, according to Moore’s Law, a key scaling concept for electronic devices, guaranteeing increasing processing power—but there is a limit.

Today’s most powerful processors have approximately 50 billion transistors in an area the size of a single thumbnail. According to Penn State experts, the job of fitting even more transistors into that tight region has grown increasingly tough.

Saptarshi Das, an Associate Professor of Engineering Science and Mechanics and co-corresponding author of the study, and his colleagues propose a solution in a study published on January 10th, 2023 in the scientific journal Nature: smoothly integrating 3D integration with 2D materials.

Within the semiconductor industry, 3D integration refers to the vertical stacking of several layers of semiconductor components. This method not only makes it easier to fit more silicon-based transistors onto a computer chip—a process known as “More Moore”—but it also makes it possible to use transistors made of two-dimensional materials to incorporate different functionalities within different layers of the stack—a concept known as “More than Moore.”

Through the work described in the study, Saptarshi and the team show that there are practical ways to accomplish More Moore and More than Moore through monolithic 3D integration, in addition to scaling existing technology. Instead of stacking separately manufactured layers as in the past, researchers that use monolithic 3D integration construct the devices directly on top of each other.

Monolithic 3D integration offers the highest density of vertical connections as it does not rely on bonding of two pre-patterned chips — which would require microbumps where two chips are bonded together — so you have more space to make connections.

Najam Sakib, Study Co-Author and Graduate Research Assistant, Pennsylvania State University

However, Darsith Jayachandran, a graduate research assistant in engineering science and mechanics and co-corresponding author of the study, points out that monolithic 3D integration presents substantial problems because traditional silicon components would melt at processing temperatures.

One challenge is the process temperature ceiling of 450 degrees Celsius (C) for back-end integration for silicon-based chips — our monolithic 3D integration approach drops that temperate significantly to less than 200 C. Incompatible process temperature budgets make monolithic 3D integration challenging with silicon chips, but 2D materials can withstand temperatures needed for the process.

Darsith Jayachandran, Study Co-Corresponding Author and Graduate Research Assistant, Pennsylvania State University

Although the researchers employed pre-existing methodologies, they are the first to accomplish monolithic 3D integration at this scale by employing transition metal dichalcogenides, a type of 2D semiconductor, to create 2D transistors.

It is about adding new and useful features to our electronic devices, like better sensors, improved battery management or other special functions, to make our gadgets smarter and more versatile.

Muhtasim Ul Karim Sadaf, Graduate Research Assistant, Pennsylvania State University

More energy-efficient computing was also made possible by the 3D integration’s ability to vertically stack the devices, which resolved an unexpected issue for such tiny components as transistors on a computer chip: distance.

 By stacking devices vertically on top of each other, you're decreasing the distance between devices, and therefore, you're decreasing the lag and also the power consumption.

Rahul Pendurthi, Study Co-Corresponding Author and Graduate Research Assistant, Pennsylvania State University

The researchers were able to obtain “More Moore” by reducing the distance between devices. Additionally, the researchers satisfied the "More than Moore" requirement by utilizing transistors constructed of two-dimensional materials.

The special optical and electrical characteristics of 2D materials, such as their light sensitivity, make them perfect for use as sensors. The researchers claimed that this is helpful given the growing number of edge devices and linked gadgets, such as wireless home weather sensors and cell phones that collect data on the “edge” of a network.

Muhtasim Ul Karim Sadaf, graduate research assistant in engineering science and mechanics and co-author of the study, stated, “More Than Moore’ refers to a concept in the tech world where we are not just making computer chips smaller and faster, but also with more functionalities. It is about adding new and useful features to our electronic devices, like better sensors, improved battery management or other special functions, to make our gadgets smarter and more versatile.

The researchers noted that there are several more benefits to using 2D devices for 3D integration. Superior carrier mobility is one of the characteristics of semiconductor materials that describes the way an electrical charge is conveyed. Another is being extremely thin, which allows the researchers to add more computational power and more transistors to each layer of the 3D integration.

The study demonstrated 3D integration at a large scale, characterizing tens of thousands of devices, in contrast to typical academic research that uses small-scale prototypes. Das claims that this accomplishment closes the knowledge gap between academics and business and could open the way for more collaborations in which businesses use Penn State’s resources and experience in 2D materials.

The availability of high-quality, wafer-scale transition metal dichalcogenides produced by scientists at Penn State’s Two-Dimensional Crystal Consortium (2DCC-MIP), a national user facility, and US National Science Foundation (NSF) Materials Innovation Platform, made the scaling advancement possible.

Charles Ying, Program Director for NSF's Materials Innovation Platforms, added, “This breakthrough demonstrates yet again the essential role of materials research as the foundation of the semiconductor industry and US competitiveness. Years of effort by Penn State's Two-Dimensional Crystal Consortium to improve the quality and size of 2D materials have made it possible to achieve 3D integration of semiconductors at a size that can be transformative for electronics.

Das contends that this is just the beginning of technological progress.

He noted, “Our ability to demonstrate, at wafer scale, a huge number of devices shows that we have been able to translate this research to a scale which can be appreciated by the semiconductor industry. We have put 30,000 transistors in each tier, which may be a record number. This puts Penn State in a very unique position to lead some of the work and partner with the U.S. semiconductor industry in advancing this research.

Along with Das, Jayachandran, Pendurthi, Sadaf and Sakib, other authors include Andrew Pannone, Doctoral Student in Engineering Science and Mechanics; Chen Chen, Assistant Research Professor in 2DCC-MIP; Ying Han, Postdoctoral Researcher in Mechanical Engineering; Nicholas Trainor, doctoral student in materials science and engineering; Shalini Kumari, Postdoctoral Scholar; Thomas McKnight, doctoral student in materials science and engineering; Joan Redwing, Director of the 2DCC-MIP and Distinguished Professor of Materials Science and Engineering and of Electrical Engineering; and Yang Yang, Assistant Professor of Engineering Science and Mechanics.

The study was supported by the National Science Foundation and Army Research Office.

Journal Reference:

Jayachandran, D., et. al. (2023) Three-dimensional integration of two-dimensional field-effect transistors. Nature. doi:10.1038/s41586-023-06860-5.

Source: https://www.psu.edu/

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