Semiconductor Research Corporation (SRC), the world’s leading university-research consortium for semiconductors and related technologies, today announced that the University of Glasgow will help identify the best p-channel material to scale the MOSFET minimum feature size, including gate length, down to the 8-nanometer technology generation. Exploiting compound semiconductor materials, progress expected from the Glasgow research will enable scaling of faster silicon chips for an additional 4-6 years beyond previous projections. The three-year project complements the most comprehensive industry research program globally for development of the two n- and p-type channels on compound semiconductors.
Driving the need for the research is the fact that continued scaling with the industry’s current silicon material may lead to curbed chip performance. The University of Glasgow will team with SRC to extend silicon’s capabilities, facilitating continued improvements in chip performance while a replacement device is found.
At the heart of the challenge is the MOSFET, the basic unit or switch in a silicon CMOS gate which is the basis for all silicon digital circuits. The industry has relied on reducing the MOSFET minimum feature size to support continued miniaturization of integrated circuits for many generations. To sustain progress, switching speed on the chips must continue to increase. The International Technology Roadmap for Semiconductors (ITRS) requires a solution that will provide more rapid switching for turning various transistors on and off as they send signals throughout the chip.
“Being able to utilize MOSFETs in compound semiconductors has been the elusive Holy Grail of scaling for 30 years. With what we expect to accomplish with the University of Glasgow, we may be only 2-3 years away from achieving that breakthrough,” said Dr. Jim Hutchby, senior scientist for the Global Research Collaboration (GRC), a unit of the SRC that is responsible for narrowing the options for carrying CMOS to its ultimate limit. “When the day comes that Moore’s Law scaling of classical silicon CMOS slows, the benefits from our extending the silicon chip using compound semiconductors could be profound for the electronics industry. At that point, we’ll have developed with compound semiconductors a new set of materials and devices to improve both the power dissipation and speed of the historically successful CMOS technology.”
Through the industry’s collective efforts, switching speeds have grown nearly 20 percent faster each year. This has contributed to the industry’s ability to maintain the aggressive pace for increasing the functionality of chips, known as Moore’s Law. However, the capability to continue this pace will eventually slow down without implementation of new compound materials, such as indium gallium arsenide or other favored elements to replace silicon as the channel region of the MOSFET.
In order to improve carrier velocities, one of the research goals of the work in Glasgow will be to “strain” p-type compound semiconductors in much the same way that performance enhancements have been realized in silicon. Strained compound semiconductor solutions are expected to yield mobilities in the range 6,000 to 50,000 cm2/Vs, more than 10 times the values achievable in silicon, which has the potential to significantly reduce switching speeds to produce faster chips.
The Glasgow team will work in close collaboration with the Non-Classical Research Center (NCRC), launched in 2006 by SRC-GRC and led by University of California-Santa Barbara. The NCRC is working on one half of the compound semiconductor challenge to provide a sharp increase in carrier velocities in the n-channel. The aim of the new work at Glasgow will be to complete the other half of the feat by winning the search for significantly improved velocities in the p-channel, also using compound elements.
“We’re on our way to proving a new class of compound semiconductors that will provide better peak carrier velocities and lower voltages and allow the industry to supplement silicon’s critical paths for speed and power,” said Professor Iain Thayne, project leader for the Glasgow team. “A long line of applications and users will be positively impacted by the expected results of this research.”
Benefits of the research will serve chipmakers and end-users for communications, computing, gaming, automotive and consumer electronics, and a wide range of other applications that are dependent on silicon’s performance.
The three-year project will begin January 1, 2008, with a total investment of US$2.5 million. The research will complement and enhance work which the University of Glasgow is already undertaking in this area, supported by the UK Engineering and Physical Sciences Research Council.
Combined with the new research funding at Glasgow, SRC-GRC has committed US$10 million to non-classical semiconductor advancement. With a goal of scaling CMOS critical dimension (i.e., gate length) down to 8 nanometers, SRC-GRC conducts the largest and most comprehensive global program dedicated to compound semiconductor ICs. SRC-GRC’s work includes the world’s leading exploration devoted to development of both the n- and p-channels via compound semiconductors.
Per its charter, SRC-GRC will continue to take a lead role in collaborating on enhancements to the academic research agenda for materials and processes associated with semiconductor manufacturing.