Jun 21 2008
Semiconductor Research Corporation (SRC), the world's leading university-research consortium for semiconductors and related technologies, today joined with researchers at Stanford University to announce multiple 'firsts' demonstrated with carbon nanotubes (CNTs) to produce CMOS-compatible working circuits on a wafer scale. CNT Field-effect Transistors (FETs) are considered contenders for extending current CMOS technology to create higher-level chip capability.
The research is funded by the Focus Center Research Program (FCRP), a subsidiary of SRC.
Efforts to perfect CNT technology to the point necessary to be considered for affordable and practical application in computer chips have been underway since the first CNT transistor was demonstrated one decade ago.
The Stanford research presented yesterday at the 2008 Symposia on VLSI Circuits and Technology in Honolulu, Hawaii, has yielded progress toward this goal that includes:
- Demonstration of full-wafer-scale growth of directional CNTs on single-crystal quartz wafers;
- Demonstration of full-wafer-scale CNT transfer from quartz wafers to silicon wafers for integration on silicon;
- Fabrication of logic structures that are immune to mispositioning of CNTs. These complex logic structures include NAND, NOR, AND-OR-INVERT and OR-AND-INVERT on a full-wafer-scale.
The accomplishments are rooted in the Stanford team's invention of a design technique that creates logic cells which function correctly even in the presence of mispositioned CNTs.
"At the nanoscale, it's nearly impossible to guarantee that all carbon nanotubes will be placed at correct positions and aligned to create a functional circuit. So the question is: if we can't control these layout requirements, how can we create working circuits?" noted Betsy Weitzman, director of FCRP. "This exciting research has brought forward a significant breakthrough for the application of CNTs in CMOS circuits -- very efficient and effective design solutions that don't require super-precise placement of the CNTs. The Stanford researchers developed an inexpensive design flow that is compatible with CMOS processing and have demonstrated that their designs can be fabricated at VLSI scale. This can clearly facilitate a breakthrough for future CMOS chip technologies."
Progress from the research could benefit chipmakers and their customers who need more advanced chips for communications, computing, security, automotive and consumer electronics, and a wide range of other applications that are dependent on silicon chip performance.
"This is the first time that anyone has experimentally demonstrated that it is possible to fabricate robust, imperfection-immune CNT-based circuits at full wafer-scale without paying the price of expensive defect and fault-tolerance techniques," said Professor Subhasish Mitra of Stanford. "The fact that these techniques are compatible with VLSI processing and have minimal impact on VLSI design flows can contribute significantly to continued advancement of Moore's Law."
Joining Professor Mitra in the research are Stanford engineering students Nishant Patil and Albert Lin, Stanford research staff member Edward Myers, and electrical engineering Professor H.-S. Philip Wong.
"Our progress potentially brings the academic and industrial communities an important step closer to the day when carbon nanotube technologies can supplement silicon CMOS technology as the technology of choice for the semiconductor industry," said Wong.
Per its charter, SRC-FCRP will continue to take a lead role in collaborating on enhancements to the academic research agenda for materials and processes associated with semiconductor manufacturing.