Dec 2 2008
From the SEMICON Japan Conference -- ATMI, Inc. (Nasdaq:ATMI), today launched PlanarClean(tm), a new generation of post-Chemical Mechanical Planarization (CMP) cleaning solutions specifically designed for advanced technology nodes, including 22 nanometer (nm), and integrating copper with low-k dielectric.
In qualification tests at nine semiconductor fabrication facilities, the PlanarClean solution was found to:
- Reduce copper roughness 67-96 percent versus traditional post-CMP cleaning solutions.
- Substantially extend the time in-process wafers can wait in queue -- by up to 3x in one case.
- Produce superior electrical performance as measured by Time-Dependent Dielectric Breakdown (TDDB), Voltage Ramp Breakdown (VRBD), and Electromigration.
The PlanarClean solution also accommodates a wide variety of post-CMP cleaning needs -- this single material formulation can handle all technology nodes from 130nm down to 22nm, and it can remove particles, metal, and organic matter without damaging copper film. In addition, the PlanarClean solution is compatible with all leading CMP equipment platforms, and greatly reduces hazardous waste production.
Shrinking circuitry creates post-CMP cleaning challenges and need for new approach
The PlanarClean solution was developed in response to two important industry trends: the move to smaller technology nodes, and the challenges of integrating copper with low-k dielectric materials. Both allow semiconductor manufacturers to fit a greater quantity of high-precision electronics on silicon wafers, but each presents post-CMP cleaning and polishing challenges. Traditional post-CMP cleaning solutions fell short in meeting these new challenges.
"About a year ago, as ATMI customers began testing 32nm and 22nm nodes, they started to share concerns about post-CMP cleaning effectiveness," said Damo Srinivas, ATMI Vice President, Interconnect Technologies. "Using our High Productivity Development approach based on combinatorial screening, we were able to very quickly develop a new chemistry set that allows customers to perform highly effective polishing on the most intricate circuitry. Add to that the benefit of extending the time wafers can wait in queue which reduces time pressure on the manufacturing line, combined with the improved electrical performance, and you can see why our customers are pleased with our PlanarClean solution."
Srinivas noted that the PlanarClean formulation is the first formally commercialized output from ATMI's High Productivity Development(tm) initiative that includes using combinatorial science on a wafer to drastically reduce development time and costs. He added that the approach and technology "enabled us to develop the PlanarClean solution in a fraction of the time it might have taken otherwise, giving us a nice head start in this market and demonstrating the impact this approach can have on our business."
ATMI has filed patent applications covering the PlanarClean solution, which is available for qualification testing now and will be available for high-volume shipment in Q1 2009. ATMI is featuring PlanarClean at this week's SEMICON Japan conference, taking place in Chiba from Dec. 3-5, at Exhibit Hall 8, Booth D-906. The company will also feature its:
- High Productivity Development capabilities.
- AutoClean(r) System for automated Ion Implanter cleaning (winner of the 2007 R&D 100 Award).
- RegenSi(tm) Wafer Reclaim solution.
- CMPlicity(tm), a unique, on-demand slurry management solution..