The transistor, an invention that heralded a new era in electronics, is the key component of practically all integrated circuits (ICs) and microprocessors. The point-contact transistor that Walter H. Brattain, an American Physicist and Nobel Laureate, invented in 1947 on a chunk of germanium underwent numerous phases of metamorphosis in its architecture, size and performance. Following Gordon E. Moore's law, the size of a transistor in an IC has been shrinking dramatically over the decades and has eventually been reduced to a staggering 32-nm node, for example, in Intel's 6 Core i7-980x processors1.
To cope with the ever-increasing demand for smaller, smarter and faster gadgets, the chip makers are endeavoring to scale them down further. In fact, both Intel and Nvidia have predicted the emergence of an 11-nm process technology within the next five years2. But how long will the complementary metal oxide semiconductor (CMOS) downscaling continue to be sustainable? What are the major stumbling blocks ahead?
CMOS Scaling Challenges
Fabrication intricacies do not pose the only challenge to scaling. While the deployment of next-generation immersion lithography with double patterning, extreme ultraviolet (EUV) lithography or other innovative techniques could probably do the job, other key considerations need to be addressed.
The most significant scaling limit is expected to be introduced by the static power dissipation associated with the various leakage mechanisms. As the device dimensions shrink, quantum tunneling of carriers through the gate insulator and the body-to-drain junction is poised to be predominant; rendering the circuits non-functional. At this point, conventional CMOS technology is likely to hit the wall, forcing the chip makers to hunt for alternative materials and hybrid technology platforms.
Alternative Platform, Novel Fabrication Strategy
Recent advances in nanomaterials research have propelled the exploitation of quasi-1D materials such as carbon nanotubes and semiconducting nanowires (or nanorods) to develop novel device architectures3,4. Due to the quantum transport phenomena, nanomaterial-based devices exhibit astounding properties, some of which are unprecedented for silicon5-7. Nevertheless, the lack of controlled assembly, fabrication intricacies and low throughput pose persistent challenges to the advancement from a single device to a functional circuit. The objective of our research at the Institute of Bioengineering and Nanotechnology (IBN) is to address one of these critical challenges, i.e. the fabrication throughput, which is severely compromised in conventional techniques such as electron-beam (e-beam) lithography8.
Motivated by the fact that a focused dual-beam (electron beam and ion beam) system can deposit metals and insulators in situ without the need for any pre-indexing or resist patterning9, we explored the feasibility of producing discrete, as well as integrated device elements with higher throughput (Fig. 1). Although the fabrication of transistors and other circuit elements using a dual-beam system is still a sequential process, the resist-free, direct-write technique substantially reduces the number of process steps, which in turn contributes to the process yield.
Figure 1. An artistic representation of a dual-beam (electron- and ion-beam) system engaged in direct-writing of nanoscale electronic circuits. The resist-free technique minimizes the number of process steps as compared to that involved in e-beam lithography.
Direct-Write Fabrication of Individual Field-Effect Transistors
Using a novel strategy, we have successfully demonstrated the resist-free fabrication of both depletion-mode (D-mode) and enhancement-mode (E-mode) field-effect transistors (FETs) on single-crystalline ZnO nanowires10. The D-mode or 'normally on' FETs are well suited for low-cost, pre-regulator applications, which are tolerant of high voltage drops and power dissipation between the power source and the output regulator stage. On the other hand, the E-mode or 'normally off' FETs offer the advantage of low off-state leakage current, which is of paramount significance for modern wireless devices.
The layouts of D-mode and E-mode FETs fabricated on identical ZnO nanowires are schematically illustrated in Fig. 2. The source (S) and drain (D) ohmic contacts to each nanowire were made by focused ion-beam (FIB)-deposited Pt strips (gray colored), and connected to the micropatterned Au electrodes and bonding pads. For the D-mode FET, the gate electrode (G) at the center consisted of FIB-deposited Pt and was isolated from the nanowire channel by an insulating layer (light blue colored). A partial depletion of the channel was observed under equilibrium (zero bias) condition. With the application of a gradual negative gate bias, the channel current decreased and finally ceased at a gate voltage around -3.4 V, the threshold voltage for the D-mode FET.
Figure 2. Schematic drawings of the depletion mode and the enhancement mode FETs fabricated on ZnO nanowires
In the case of an E-mode transistor, however, the gate electrode was composed of platinum (brown in the schematic), which had been directly deposited on ZnO nanowire by focused electron-beam (FEB) and formed a Schottky-gated MESFET. The depletion layer approximation predicts that a nanowire with a diameter of 80-90 nm should be fully depleted by a Ù-shaped surrounding top gate that makes a Schottky contact to the channel. In fact, a leakage current ~10-13A was measured at zero gate bias. From the transfer characteristics curve, the values of threshold voltage, trans-conductance (gm) and on-off ratio were calculated to be 1.1 V, 55 nS and > 106, respectively.
A Step Toward Integration
After characterizing the individual E- and D-mode transistors on discrete but identical ZnO nanowires, we made an attempt to integrate the two types of FETs on a single nanowire to derive the functionality of a logic inverter (Fig. 3). An elementary logic inverter consists of an active switching device, or 'driver', in series with a 'load' device. An E-mode transistor is preferred for use as a driver as the use of a D-mode driver would require an additional level-shifter to make the input and output voltage levels of the logic gate compatible. Conversely, a D-mode transistor is preferred as a load because depletion-load inverters exhibit (i) sharp voltage transfer characteristics (VTC) transition and better noise margin, (ii) single power supply, and (iii) smaller overall layout area.
Figure 3 schematically depicts the circuit of a depletion-load inverter. For a supply voltage of +5 V, the transition from 'logical 1' to 'logical 0' state occurs at around 2.1 V. The voltage gain of the inverter increased with the magnitude of VDD and reached a value of about 29 for VDD = 10.0 V, while the noise margins for high and low signal levels were 2.52 V and 1.46 V, respectively.
Figure 3. Schematic diagram of a DCFL inverter fabricated on a single nanowire. The platinum electrodes were 'directly written' using either focused ion beam (gray) or electron beam (brown). Microfabricated Au contact leads and bonding pads were used for interfacing the devices with the macro world. The blue layer beneath one of the Pt gate electrodes indicates the in situ deposited silicon oxide layer.
In conclusion, IBN's single-step fabrication technique obviates the time-consuming and labor-intensive lithography process for nano-scale device fabrication, and enhances the fabrication accuracy and yield. With a higher level of precision and throughput, the direct-write technique can offer a powerful method for rapid prototyping of futuristic nanoelectronic circuits.
1. Intel® Core™ i7-980X Processor Extreme Edition: http://ark.intel.com/Product.aspx?id=47932
2. http://www.eetimes.com/electronics-news/4087879/SPIE-Intel-to-extend-immersion-to-11-nm; http://www.eetimes.com/electronics-news/4084065/Nvidia-chief-scientist-to-EDA-Give-us-power-tools
3. S. J. Tans, A. R. M. Verschueren and C. Dekker "Room-Temperature Transistor Based On a Single Carbon Nanotubes," Nature, 393 (1998) 49
4. Z. Zhong, D. Wang, Y. Cui, M. W. Bockrath and C. M. Lieber, "Nanowire Crossbar Arrays as Address Decoders for Integrated Nanosystems", Science, 302 (2003) 1377 (2003)
5. A. Javey, Q. Wang, A. Ural, Y. Li and H. Dai. "Carbon Nanotube Transistor Arrays for Multistage Complementary Logic and Ring Oscillators," Nano Letters, 2 (2002) 929
6. D. Kim, J. Huang, H. Shin, S. Roy and W. Choi, "Transport Phenomena and Conduction Mechanism of Single-Walled Carbon Nanotubes (SWNT) at Y- and Crossed Junctions," Nano Lett., 6 (2006) 2821
7. Y. Cui, C. M. Lieber, "Functional Nanoscale Electronic Devices Assembled Using Silicon Nanowire Building Blocks," Science, 291 (2001) 851
8. Z. Chen, J. Appenzeller, Y.-M. Lin, J. Sippel-Oakley, A.G. Rinzler, J. Tang, S.J. Wind, P. M. Solomon and P. Avouris, Science, 311 (2006) 1735
9. I. Utke, P. Hoffmann, J. Melngailis, "Gas-Assisted Focused Electron Beam and Ion Beam Processing and Fabrication," J. Vac. Sci. Technol. B, 26 (2008) 1197
10. S. Roy and Z. Gao, "Direct-Write Fabrication of a Nanoscale Digital Logic Element on a Single Nanowire," Nanotechnology, 21 (2010) 245306
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