Nanoelectronics News

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Press Conference on Harnessing Everyday Motion to Power Mobile Devices on March 17

Imagine powering your cell phone by simply walking around your office or rubbing it with the palm of your hand. Rather than plugging it into the wall, you become the power source. Researchers at the 247th National Meeting & Exposition of the American Chemical Society (ACS), the world's largest scientific society, presented these commercial possibilities and a unique vision for green energy.

From American Chemical Society 17 Mar 2014

Research and Markets Adds Report on Graphene Materials for Opto & Electronic Applications

Research and Markets has announced the addition of the "Graphene Materials for Opto & Electronic Applications 2014" report to their offering.

From Research and Markets 17 Mar 2014

NSSA Honors Emil Bozin for Discovering Broken Symmetries in Exotic Electronic Materials

The Neutron Scattering Society of America (NSSA) has named Emil Bozin, a condensed matter physicist at the U.S. Department of Energy's Brookhaven National Laboratory, the recipient of their 2014 Science Prize. The NSSA award specifically recognized Bozin's discovery of "broken symmetry local structures in exotic electronic materials, his elaboration of their nature and their importance to the material properties, in particular in PbTe, iridates, manganites, and cuprates."

17 Mar 2014

Mikron to Leverage Cadence EDA Tools for 90 nm IC Design Flow

Cadence Design Systems, Inc., a leader in global electronic design innovation, and JSC Mikron, the largest manufacturer and exporter of microelectronics and RFIDs in Russia and CIS (Community of Independent States), part of the industrial holding “RTI Systems”, announced today that Mikron has licensed Cadence® Physical Verification System (PVS) and Cadence QRC Extraction to be used in Mikron’s basic 90nm IC design flow.

From Cadence Design Systems 14 Mar 2014

GLOBALFOUNDRIES Certifies Cadence PVS for 65nm to 14nm FinFET Process Technologies

Cadence Design Systems, Inc., a leader in global electronic design innovation, announced today that GLOBALFOUNDRIES certified the Cadence® Physical Verification System (PVS) for custom/analog, digital and mixed-signal design physical signoff for 65nm to 14nm FinFET process technologies.

From GlobalFoundries 13 Mar 2014

Surface Topography and Chemistry Can Influence Cellular Behavior on Semiconductors

Changing the texture and surface characteristics of a semiconductor material at the nanoscale can influence the way that neural cells grow on the material.

From North Carolina State University 13 Mar 2014

Cadence, GLOBALFOUNDRIES Tape Out Quad Core Test Chip Built Around ARM Cortex-A12 Processor

Cadence Design Systems Inc. and GLOBALFOUNDRIES announced that they have taped out a quad core test chip built around the ARM Cortex-A12 processor. Targeted to operate at frequencies of up to 2.0GHz while still within the mainstream mobile power and area envelope, the test chip is implemented in GLOBALFOUNDRIES’ 28nm-SLP (Super Low Power 28 nanometer High-K Metal Gate) process using a full Cadence® tool flow and incorporates ARM POP™ technology to leverage the full performance range of the 28-SLP process.

From GlobalFoundries 13 Mar 2014

IC Plus Selects Analog FastSPICE Platform for Full-Circuit Verification of their Mixed-Signal Ics

Berkeley Design Automation, Inc., provider of the world’s fastest nanometer circuit verification, today announced that IC Plus Corporation, a communication and networking IC design company has selected the Analog FastSPICE Platform for full-circuit verification of their mixed-signal integrated circuits.

12 Mar 2014

Broadcom Unveils BCM82322 Lite-PHY Fabricated in 28nm CMOS Technology

Broadcom Corporation, a global innovation leader in semiconductor solutions for wired and wireless communications, today announced the industry's first triple speed 10/40/100G Lite physical layer transceiver (Lite-PHY) designed for high-density data center applications.

12 Mar 2014

CEA-Leti Fabricates Ultra-Scaled Split-gate Memories with Gate Length of 16nm

CEA-Leti announced today it has fabricated ultra-scaled split-gate memories with gate length of 16nm, and demonstrated their functionality, showing good writing and erasing performances with memory windows over 6V.

From CEA-Leti 12 Mar 2014

Nanoelectronics News

Press Conference on Harnessing Everyday Motion to Power Mobile Devices on March 17

Research and Markets Adds Report on Graphene Materials for Opto & Electronic Applications

NSSA Honors Emil Bozin for Discovering Broken Symmetries in Exotic Electronic Materials

Mikron to Leverage Cadence EDA Tools for 90 nm IC Design Flow

GLOBALFOUNDRIES Certifies Cadence PVS for 65nm to 14nm FinFET Process Technologies

Surface Topography and Chemistry Can Influence Cellular Behavior on Semiconductors

Cadence, GLOBALFOUNDRIES Tape Out Quad Core Test Chip Built Around ARM Cortex-A12 Processor

IC Plus Selects Analog FastSPICE Platform for Full-Circuit Verification of their Mixed-Signal Ics

Broadcom Unveils BCM82322 Lite-PHY Fabricated in 28nm CMOS Technology

CEA-Leti Fabricates Ultra-Scaled Split-gate Memories with Gate Length of 16nm

Magnetic Nanocarbon Composite Cleans Chernobyl’s Wastewater

Double-Layer Design Boosts Charge and Range of EV Batteries

Dark Nanoparticles Make Kidney Stone Removal Faster and Safer

Explore PI’s Precision Motion Innovations for Life Sciences at Neuroscience 2025

Minimal Pixels Achieve the Highest Possible Resolution Visible to the Human Eye

Enhancing Slurry Stability in Lithium-Ion Batteries with Turbiscan Technology

PiFM and its Role in Nanoscale Chemical Imaging

Conversations on AFM: How AI is Automating Scanning Probe Microscopy

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