Posted in | Nanoelectronics

Nangate’s New Footprint Compatible Module Help Improve Performance of Digital Designs

Nangate Inc, the leading supplier of digital cell library development and design optimization solutions, today announced the release of the Footprint Compatible module, a solution enabling power reduction and faster timing closure when used with Nangate Design Optimizer™ and MegaLibrary™.

The Footprint Compatible module solution will enhance existing standard cell libraries in conjunction with Nangate Library Creator™.

The Footprint Compatible module allows digital designers to improve the performance of digital designs and increase the efficiency of the physical implementation process by introducing fine grain footprint compatible combinational cell variants into the flow. The solution is very efficient for late-stage speed and power optimization enabling fine-tuned cell-sizing to be performed even post-route and is P&R tool agnostic.

“Many of our customers, especially at 40nm where process speed has not seen an appreciable increase over 65nm, are experiencing severe trouble closing timing in the very last stages with traditional flows and libraries,” says Jens Michelsen, VP Professional Services and Nangate Co-founder. “With Nangate’s Footprint Compatible module, customers can more rapidly close design timing, saving weeks of engineer effort as well as gaining the last few percent of frequency performance that is essential for success in the next generation of CPU core, wireless and networking applications.”

Using the Footprint Compatible Module solution, leakage power reduction is achieved by performing in-place-optimization (IPO) using fine-grained channel length optimized variants of commonly used cells without disrupting final timing and physical routing. Designs which are very difficult to close on critical timing with traditional flows benefit from late-stage IPO using footprint compatible drive-strength and skew variants, a particularly efficient method that does not disrupt existing metal routing and parasitics.

"At NXP, we leapt from 90nm to 45nm to create the world’s first 45nm SOC for digital consumer. It was a large and complex platform and the cost advantage of 45nm was considerable. However at 45nm, design boundaries are narrowing, increasing variability and parasitic effects and high power density and leakage considerations. Timing closure is a real headache," commented Andrew Appleby, formerly Physical Design Manager at NXP Semiconductors, now at CSR Ltd. "The ability to do extensive post route optimization, without disrupting routing parasitics, particularly in areas of high congestion is the key to smooth design closure. It’s analogous to performing key-hole surgery…no painful collateral damage! Footprint compatible ECO cells are a powerful and flexible way to unlock the problem, reduce ECO cycles and development costs."

“We are very excited about the release of the Footprint Compatible module,” says Ole C. Andersen, Co-founder and CEO at Nangate Inc. “It further extends Nangate’s existing design optimization solutions and enables today’s digital designers to achieve higher performance and lower power designs with greater efficiency.”


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