Cadence Design Systems makes improvements to its Virtuoso-based analog flow. This increases productivity for the flow from the basic design to the final GDSII, and for process nodes down to 20 nanometers.
The expanded flow includes enhanced methodology to help control design parasitics, a DFM capability, and an integrated Virtuoso power system, to provide an accurate way to control problems relating to power and signal integrity. These developments enhance designer productivity.
The integrated flow increases in-design DFM capabilities of the Virtuoso environment that detect and solve DFM violations during the design process, helping designers address production issues. The Cadence Virtuoso Power System helps control IR fluctuation and electromigration related issues including shorts and hotspots. Parasitic-aware designs can detect implementation effects earlier.
Editing, automation, and estimation provide combined intent, convergence and abstraction needed for maximum Silicon Realization. These features provide increased global data-sharing and seamless technology integration.
A waveform viewer removes the need for external tools. The system features automated constraint monitoring, an editing engine for complicated node rule sets and an interactive short detector that helps to find and fix faults in layout-versus-schematic faults.