Synopsys, a company that provides IP and software to design and manufacture semiconductors, declared that its design enablement partnership with Samsung Electronics has resulted in the successful release of the 20 nm test chip implemented using the High-k metal gate (HKMG) process technology from Samsung.
Using the Synopsys' galaxy implementation platform, the implementation of the test chip was performed, wherein the platform includes the IC compiler place-and-route, design compiler synthesis, StarRC extraction, PrimeTime signoff tools, and In-Design physical verification with IC validator.
The tapeout of 20-nm test chip is a result of the R&D collaboration between the two companies to develop and test a complete design execution infrastructure for the advanced gigascale integrated circuits at 20-nm. The vital 20-nm design advancements developed include double-patterning-aware place-and-route, modeling of innovative equipment structures, coding of modern routing and design rule checking (DRC), and in-design physical verification technology. These innovative technologies allow fast routing throughput while maintaining complete compliance to routing patterns and complicated regulations.
The VP of System LSI infrastructure design center, Device Solutions, Samsung Electronics, Dr. Kyu-Myung Choi, stated that the successful rollout of the test chip shows that a crucial milestone with regards to their 20-nm process technology being design-ready has been reached
Source: http://synopsys.mediaroom.com/