Tiempo together with STMicroelectronics has designed a first-of-its-kind 32-nm fully clockless circuit, which was produced as a first-time-right silicon chip.
The test chip shows a clockless circuit’s unprecedented advantages for advanced process technology nodes. The combination of Tiempo’s delay-insensitive method and 16-bit microcontroller (TAM16) enables the test chip to operate over a broad voltage range in all places of the process, irrespective of the observed process variability and wafer position.
STMicroelectronics’ 32 nm Design Platform was utilized to design the test chip. The platform now features an asynchronous standard cell library, which was created by STMicroelectronics in collaboration with Tiempo and CEA-Leti. SystemVerilog was used to model the test chip and then Tiempo Asynchronous Circuit Compiler was used to synthesize the test chip, which then placed-and-routed utilizing typical back-end tools.
According to STMicroelectronics’ Technology R&D Design Department Manager, Robin Wilson, Tiempo’s design process facilitates the integration of the TAM16 microcontroller on a sophisticated CMOS process utilizing typical EDA tools. Moreover, TAM16 can operate over a broad voltage range and does not require any extra design effort for this operation. It is necessary to compensate for process variability in the development of advanced processes. To design conventional clocked circuits, considerable margins need to be allowed in order to make the chip functional.
Tiempo’s Chief Executive Officer, Serge Maginot stated that these problems have been solved by Tiempo’s clockless approach as each chip runs at its optimal speed based on the qualities of silicon and production. The company intends to provide a clockless approach to offer important feedback for EDA-vs-silicon correlation and technology performance characterization for even more advanced process nodes.
Source: http://www.tiempo-ic.com