STATS ChipPAC Ltd. (“STATS ChipPAC” or the “Company”), a leading provider of advanced semiconductor packaging and test services, today announced that it has been granted its 1,000th patent by the U.S. Patent and Trademark Office (USPTO).
Since the inception of its Intellectual Property (IP) program in 2000, STATS ChipPAC has filed more than 1,500 patents and published patent applications with the USPTO and more than 900 patents and applications in other countries, of which more than 200 have been registered or allowed as patents in Singapore, South Korea, Taiwan and other countries. This is at least 400 more U.S. patents and applications than other companies in the global Outsourced Semiconductor Assembly and Test (OSAT) industry. STATS ChipPAC has concentrated its IP development on advanced or future technologies such as wafer level packaging, Post Wafer fab Processing (PWfP) or mid-end processing, Through Silicon Via (TSV), flip chip interconnect, integrated passive devices (IPD) and 2.5D/3D package integration. With this strategic focus, STATS ChipPAC has built up a patent portfolio in which advanced or future technologies comprise 60% of its IP.
STATS ChipPAC’s patent portfolio has been recognized for its quality, strength and overall importance to the semiconductor manufacturing industry by The Institute of Electrical and Electronics Engineers (IEEE), the world’s largest professional association for the advancement of technology. IEEE ranked STATS ChipPAC among the top 10 semiconductor manufacturing companies in the world for the last two consecutive years based on the strength of its IP and technology innovations.
“Our 1,000th U.S. patent is a milestone achievement for STATS ChipPAC. Over the last 5 to 10 years, we have demonstrated our commitment to technology innovation and built a high-quality, innovative IP portfolio. In 2011, we became the leading patent holder among our competitors worldwide in terms of the number of U.S. patents granted and have continued to develop advanced technology and process improvements that will drive evolutionary packaging for our customers,” said Dr. Han Byung Joon, Executive Vice President and Chief Technology Officer, STATS ChipPAC.
STATS ChipPAC’s 1,000th U.S. patent is a strong representation of the priority the Company has placed on the development of advanced wafer level technology. U.S. Patent No. 8,456,002, “Semiconductor Device and Method of Forming Insulating Layer Disposed Over the Semiconductor Die for Stress Relief”, relates to innovations in the assembly of embedded Wafer Level Ball Grid Array (eWLB) devices in which an insulating layer provides stress relief during the formation of an interconnect structure in the device. This is part of a family of patents that includes five previously granted U.S. patents for eWLB and Wafer Level Chip Scale Packaging (WLCSP) inventions.
Dr. Han continued, “This milestone patent is further recognition not only of our rapidly evolving wafer level technologies, but also of our dedication and leadership in developing innovative technologies that provide solutions for the challenges confronting semiconductor packaging today.”