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VLSI 2015 Symposia: imec to Present Record Number of 11 Papers

At this year’s on VLSI Technology and Circuits (June 15-19, 2015), nano-electronics research center imec will present a record number of 11 papers. Imec’s prominent presence at this renowned scientific meeting confirms its leading role in R&D on tackling the challenges to scale logic and memory architectures, and on advanced circuit design solutions.

Next to a record number of papers, imec also contributes with 3 invited talks and1 short course lecture, in panel discussions and with four papers with imec scientists as co-authors. Highlights are a record-performing germanium p-channel FinFET, an active interposer for better 2.5/3D integration, and promising achievements on resistive switching memory devices (RRAM). Imec’s Aaron Thean will deliver an invited talk on nanodevice enablers for emerging applications and the role of an ultra-low leakage switch, Jo De Boeck’sinvited talk is titled: the internet of things (IoT): the Impact of Things and An Steegen is invited to talk about technology innovation in an IoT Era.. In the Circuits Symposium, imec will present a digitally-tunable radio SoC with integrated digital baseband and MAC Processor in 40nm CMOS.

“Imec has participated in the VLSI conference for almost a decade and a half, with a growing importance and impact,” stated Luc Van den hove, president and CEO at imec. “I am elated with the large delegation of imec researchers taking part in this year’s edition. It underscores our commitment to stay at the forefront of research and support our global partner network with innovative solutions.”

Overview of imec’s presentations at the 2015 VLSI symposia:

June 15

  • 9.30 –Short course - Logic Nano-Device Enablers for Emerging Applications & The Role of Ultra-Low Leakage Switch, A. Thean, imec

June 16

  • 10.55 - Highly Reliable TaOx ReRAM with Centralized Filament for 28-nm Embedded Application, Hayakawa, A. et al. (Panasonic)
  • 13.30 AC NBTI of Ge pMOSFETs: Impact of Energy Alternating Defects on Lifetime Prediction;Ma, J. et al.(Liverpool John Moores Univ)
  • 13.55 A Test-Proven As-Grown-Generation (A-G) Model for Predicting NBTI under Use-Bias;Z. Ji, Z. et al.(Liverpool John Moores Univ)
  • 14.20 Vertical Device Architecture for 5nm and Beyond: Device and Circuit Implications;Thean, A et al.
  • 14.45 15-nm Channel Length MoS2 FETs with Single- and Double-Gate Structures; Nourbakhsh, A. et al. (KU Leuven)
  • 15.10 A comparison of arsenic and phosphorus extension by room temperature and hot ion implantation for NMOS Si bulk-finFET at N7 (7nm) technology relevant fin dimensions; Sasaki, Y. et al.
  • 15.50 Strained germanium quantum well p-finFETs fabricated on 45nm fin pitch using replacement channel, replacement metal gate and germanide-free local interconnect; Witters, L. et al.
  • 16.40 Characterization of self-heating in high mobility Ge finFET pMOS devices; Bury, E. et al.

June 17

  • 10.55 – Invited- IoT: the Impact of Things;de Boeck, J.
  • 13.55 A 3.5mW 315/400MHz IEEE802.15.6/Proprietary Mode Digitally-Tunable Radio SoC with Integrated Digital Baseband and MAC Processor in 40nm CMOS;Bachmann, C. et al.
  • 16.15 Gate-all-around NWFETs vs. triple-gate finFETs: junctionless vx extensionless onventional junction devices with controlled EWF modulation for multi-VT CMOS; Veloso, A. et al.
  • 17.05 a-VMCO: a novel forming-free, self-rectifying, analog memory cell with low-current operation, nonfilamentaryswitching and excellent variability; Govoreanu, B. et al.
  • 17.05 Si-cap-free SiGe p-channel finFETs and gate-alle-around transistors in a replacement metal gate process: interface trap density reduction and performance improvement by high-pressure deuterium anneal; Mertens, H. et al.
  • 17.30 A novel CBRAM integration using subtractive dry-etching process of Cu enabling high-performance memory scaling down to 10nm node; Redolfi, A. et al.

June 18

  • 8.30 RMG nMOS 1st process enabling 10x lower gate resistance resistivity in N7 bulk finFETs; Ragnarsson, L.A. et al.
  • 12.10 Quantitative endurance failure model for filamentary RRAM; Degraeve, R. et al.
  • 14.20 – Invited - Technology Innovation in an IoT Era;Steegen, A.
  • 16.15 Active-lite interposer for 2.5&3D integration; Helings, G. et al.

For more information, attend imec’s presentations at VLSI 2015

This Press release can be downloaded at


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