Thought Leaders

Carbon Nanomaterials for Designing Next-Generation Green Electronics

Low-dimensional allotropes of carbon (including two-dimensional graphene and one-dimensional carbon nanotubes and graphene nanoribbons), collectively known as carbon nanomaterials, have extraordinary physical properties that can be exploited for their exciting prospects in a variety of electronics applications.

In particular, these nanomaterials can be used to design low-power, low-loss and ultra energy-efficient active and passive nanoelectronic devices, which can consequently lead to unprecedented levels of integration density and energy-efficiency in coming generations of integrated circuits and electronic products.

The structures of all carbon nanomaterials can be derived from that of graphene, which is a single-atom-thick planar sheet of sp2-bonded carbon atoms packed in a honeycomb crystal lattice (Fig. 1a).

A graphene nanoribbon (GNR) can be obtained by patterning graphene into a ribbon, while a carbon nanotube (CNT) can be thought of as a rolled up ribbon to form a seamless tube.

The band structure of graphene has unique characteristics: the energy dispersion (or simply E-k) relation is linear near the Fermi energy level, leading to zero effective mass for electrons and holes, and thereby to extremely high carrier mobility (> 10000 cm­2/V-s).

Some key properties of these carbon nanomaterials are outlined in Table I along with those of some common semiconductors and a metal (Cu), indicating their great potential in next-generation electronics applications1. In the following paragraphs, we briefly outline and highlight the prospects of carbon nanomaterials for designing next generation “green” electronics.

(a) The atomic structure of CNT and GNR derived from a graphene sheet. (b) A 2-inch wafer size graphene grown on nickel in the Nanoelectronics Research Laboratory (NRL) at UCSB. (c) Selective carbon nanotube growth used to form the pattern of NRL logo.

Figure 1. (a) The atomic structure of CNT and GNR derived from a graphene sheet. (b) A 2-inch wafer size graphene grown on nickel in the Nanoelectronics Research Laboratory (NRL) at UCSB. (c) Selective carbon nanotube growth used to form the pattern of NRL logo.







Graphene or GNR

Max current density (A/cm2)








Melting point (K)





3800 (graphite)

Tensile strength (GPa)







Mobility (cm2/V-s)


8500-9500 (for low doping)





Thermal conductivity (´103 W/m-K)








Temperature Coefficient of Resistance (´10-3 /K)








Mean free path (nm) @ room temperature


~ 300 nm (for AlGaAs/GaAs Heterostructure)

~ 20 – 30 nm (for AlGaN/GaN Heterostructure)





Table I. Properties of carbon nanomaterials (single-walled CNT (SWCNT), multi-walled CNT (MWCNT), and graphene nanoribbon (GNR)) in comparison to those of some semiconductors (Si, GaAs, and GaN) and metal (Cu) used for various electronics applications.

Low-Power High-Speed Interconnects

Metal interconnections used as communication links between billions of transistors in modern integrated circuits (ICs) have come to occupy the center stage in determining the performance and power dissipation of electronic chips such as microprocessors2,3.

A typical high-performance IC employs several layers of metal interconnects separated by insulating materials, with “short-wires” employed for local communication and “long-wires” used for global communication within a chip.

Interconnects are also used for distributing the clock signals throughout the chip and are known to be responsible for over 50% of the power dissipation in most ICs. It has been shown that the delay of global interconnects can be reduced by up to 50% if CNT bundles or multi-layer Graphene interconnects are employed4-6. Meanwhile, if the delay of CNT/Graphene interconnects are kept at the same optimal delay of metal (Cu) interconnects, CNT/Graphene interconnects would reduce the global interconnect power consumption by 50% compared to that of Cu interconnects7.

Low-Loss Passive Devices

In ultra high-frequency (millimeter wave and radio-frequency) applications, increased losses due to skin and proximity effects in IC interconnects and passive devices can also contribute significantly to reducing the energy-efficiency of electronic circuits and products.

CNT/Graphene interconnects have been shown to exhibit unique high-frequency behavior (reduced skin effect) owing to their large momentum relaxation time, indicating promising high-frequency applications8,9. For example, it has been shown that the maximum Q-factor (a metric quantifying inductor efficiency) of a ¾-turn inductor can be increased by as much as 230 % (3.3 times) and 32% (1.3 times) by replacing Cu with CNTs and graphene, respectively 8,10.

CNTs are also known to have excellent thermal properties (Table 1) and in light of the benefits they offer for ultra high-frequency operation, they are also promising as Through-Silicon Vias (TSV) 11 --a key enabling technology for 3-dimensional (3D) -ICs.

3-D ICs allow stacking and bonding of multiple active layers (substrates) and are being pursued in many semiconductor companies around the world due to their low-power prospects (resulting from their reduced interconnect lengths) and feasibility of heterogeneous integration of disparate technologies (Si, III-V, Graphene) and circuits (digital, analog, RF, optics, etc) 12.

High-Density Energy-Storage Devices

For high-density metal-insulator-metal (MIM) capacitor designs, it has been shown that the capacitance density of CNT-based capacitors can reach as high as 38.39 fF/μm2, much larger than the International Technology Roadmap for Semiconductors (ITRS) requirement of 12fF/μm2 for the year 20221, indicating their excellent potential to replace current MIM capacitors as well as other on-chip charge-storage based devices.

Graphene has also shown promise as electrode materials in supercapacitor applications due to its large surface-area to volume ratio. It has been recently reported that graphene based supercapacitors exhibit a specific energy density of 85.6 W·h/kg at room temperature, much higher than that of conventional lead-acid batteries (typically 30 to 40 W·h/kg)13.

Ultra Energy-Efficient Active Devices

More recently, the semiconductor industry has witnessed renewed interest in ultra energy-efficient transistors. This is driven by the need to find a replacement switch for the nanoscale MOSFET, which forms the work horse of the IC industry but suffers from increasingly high off-state leakage, thereby making it very energy inefficient.

A key research goal in the area of ultra energy-efficient transistor design is the design and demonstration of small subthreshold swing (SS) switches (including tunnel-field effect transistors (T-FET) and Nanoelectromechanical (NEM)-FET) that makes ON to OFF switching more abrupt and reduces leakage current, as an eventual replacement for the MOSFET14,15.

However, to make this a reality, demonstration of compact, scalable, and reliable T-FETs/NEM-FETs with high (MOSFET like) ON currents, and low OFF currents at low power-supply voltages, that are suitable for building large-scale logic circuits and systems, are highly desirable.

CNT and GNR are excellent materials for designing such energy-efficient active devices for next-generation green electronics.

For example, the high mobility and low bandgap of graphene has been exploited to design a GNR based heterojunction T-FET exhibiting ION as high as 1 mA/μm, ION/IOFF ratio as high as 109, and SS as small as 10 mV/dec at VDD=0.5 V, and Lch=20 nm16. Moreover, understanding the physics of band-to-band-tunneling (BTBT), which is key to designing T-FETs with any material, has been shown to be easily enabled by GNR based T-FETs17. On the other hand, CNT is an excellent material for designing NEM-FETs due to their low mass density and high Young’s modulus18.

High-Efficiency Photovoltaics

Efficient harvesting of solar energy through novel photovoltaic devices is critical for global scale reduction of green house gases. Hence, increasing the efficiency of photovoltaic devices has become a key research goal in the area of solar cell design.

A two orders of magnitude enhancement of photocurrent resulting from adding Single-Walled CNTs (SWCNTs) to a poly-3-octylthiophene (P3OT) matrix has been reported in an organic solar cell19.

It has also been reported that using SWCNTs as conducting scaffolds in a TiO2 based dye-sensitized solar cell can double the photoconversion efficiency20.

More interestingly, extremely efficient multiple electron-hole pair generation has been observed in CNT due to optical excitation into the second subband suggesting the possibility of exceeding the thermodynamic (Shockley-Queisser) limit21. There is also lots of interest in employing CNT/graphene as transparent electrodes for solar cell and LED applications22-24.


  1. H. Li, C. Xu, N. Srivastava, and K. Banerjee, “Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status and Prospects,” IEEE Transactions on Electron Devices, Vol. 56, No. 9, pp. 1799-1821, Sep 2009.
  2. K. Banerjee and A. Mehrotra, “Global (Interconnect) Warming,” IEEE Circuits and Devices Magazine, pp.16- 32, 2001.
  3. K. Banerjee and A. Mehrotra, “A Power-Optimal Repeater Insertion Methodology for Global Interconnects in Nanometer Designs,” IEEE Transactions on Electron Devices, Vol. 49, No. 11, pp. 2001-2007, November 2002.
  4. N. Srivastava, H. Li, F. Kreupl, and K. Banerjee, “On the Applicability of Single-Walled Carbon Nanotubes as VLSI Interconnections,” IEEE Transactions on Nanotechnology, Vol. 8, No. 4, pp. 542-559, July 2009.
  5. H. Li, N. Srivastava, W. Y. Yin, K. Banerjee, and J. F. Mao, “Circuit Modeling and Performance Analysis of Multi-Walled Carbon Nanotube Interconnects,” IEEE Transactions on Electron Devices, Vol. 55, No. 6, pp. 1328-1337, 2008.
  6. C. Xu, H. Li, and K. Banerjee, “Modeling, Analysis and Design of Graphene Nano-Ribbon Interconnects,” IEEE Transactions on Electron Devices, Vol. 56, No.8, pp. 1567-1578, 2009.
  7. H. Li, C. Xu, and K. Banerjee, “Carbon Nanomaterials: The Ideal Interconnect Technology for Next-Generation ICs,” IEEE Design and Test of Computers, Special Issue on Emerging Interconnect Technologies for Gigascale Integration, Vol. 27, No. 4, pp. 20-31, July/August, 2010.
  8. H. Li and K. Banerjee, “High-Frequency Analysis of Carbon Nanotube Interconnects and Implications for On-Chip Inductor Design,” IEEE Transactions on Electron Devices, Vol. 56, No. 10, pp. 2202-2214, 2009.
  9. D. Sarkar, C. Xu, H. Li, and K. Banerjee, “High-Frequency Behavior of Graphene-Based Interconnects – Part I: Impedance Modeling,” IEEE Transactions on Electron Devices, Vol. 58, No. 3, pp. 843-852, 2011.
  10. D. Sarkar, C. Xu, H. Li, and K. Banerjee, “High-Frequency Behavior of Graphene-Based Interconnects – Part II: Impedance Analysis and Implications for Inductor Design,” IEEE Transactions on Electron Devices, Vol. 58, No. 3, pp. 853-859, 2011.
  11. C. Xu, H. Li, R. Suaya and K. Banerjee, “Compact AC Modeling and Performance Analysis of Through-Silicon Vias (TSVs) in 3-D ICs,” IEEE Transactions on Electron Devices, Vol. 57, No. 12, pp. 3405-3417, Dec. 2010.
  12. K. Banerjee, S. J. Souri, P. Kapur, and K. C. Saraswat, “3-D ICs: A Novel Chip Design for Improving Deep Submicron Interconnect Performance and Systems-on-Chip Integration,” Proceedings of the IEEE, Vol. 89, No. 5, pp. 602-633, May 2001.
  13. C. Liu, Z. Yu, D. Neff, A. Zhamu, and B. Z. Jang, “Graphene-based Suppercapacitor with an Ultrahigh Energy Density,” Nano Letters, Vol. 10, pp. 4863-4868, 2010.
  14. H. F. Dadgour and K. Banerjee, “Hybrid NEMS-CMOS Integrated Circuits: A Novel Strategy for Energy-Efficient Designs,” IET Transactions on Computers and Digital Techniques—Special Issue on Advances in Nanoelectronics Circuits and Systems, Vol. 3, No. 6, pp. 593-608, Nov. 2009.
  15. Y. Khatami and K. Banerjee, “Steep Subthreshold Slope n- and p-type Tunnel-FET Devices for Low-Power and Energy-Efficient Digital Circuits,” IEEE Trans. Electron Devices, Vol. 56, pp. 2752-2761, 2009.
  16. Y. Khatami, M. Krall, H. Li., C. Xu., K. Banerjee, “Graphene Based Heterostructure Tunnel-FETs for Low- Voltage/High-Performance ICs,” 68th Device Research Conference (DRC), 2010, pp. 65-66.
  17. D. Sarkar, M. Krall, and K. Banerjee, “Electron-hole Duality During Band-to-Band Tunneling Process in Graphene-Nanoribbon Tunnel-Field-Effect Transistors,” Applied Physics Letters, Vol. 97, No. 26, p. 263109, 2010.
  18. H. Dadgour, A. M. Cassell and K. Banerjee, “Scaling and Variability Analysis of CNT-Based NEMS Devices and Circuits with Implications for Process Design,” IEEE International Electron Devices Meeting (IEDM), pp. 529-532, 2008.
  19. E. Kymakis, I. Alexandrou, G. A. J. Amaratunga, “High Open-Circuit Voltage Photovoltaic Devices from Carbon-Nanotube-Polymer Composites,” Progress in Photovoltaics: Research and Applications, Vol. 93, no. 3, pp. 1764–1768, 2003.
  20. A. Kongkanand, R. M. Dominguez, P. V. Kamat, “Single Wall Carbon Nanotube Scaffolds for Photoelectrochemical Solar Cells: Capture and Transport of Photogenerated Electrons,” Nano Letters, Vol. 7, no.3, pp. 676–680, 2007.
  21. N. M. Gabor, Z. Zhong, K. Bosnick, J. Park, and P. L. McEuen, “Extremely Efficient Multiple Electron-Hole Pair Generation in Carbon Nanotube Photodiodes”, Science, Vol. 325, 1367, 2009.
  22. M. W. Rowell, M.A. Topinka,; M. D. McGehee, H.-J. Prall, G. Dennler, N. S. Sariciftci, L. Hu, G. Gruner, “Organic Solar Cells with Carbon Nanotube Network Electrodes,” Applied Physics Letters, Vol. 88, no.23, 233506, 2006.
  23. X. Wang, L. J. Zhi, K. Müllen, “Transparent, Conductive Graphene Electrodes for Dye-Sensitized Solar Cells,” Nano Letters, Vol. 8, no. 1, pp. 323–327, 2008
  24. V. C. Tung, L. Chen, M. J. Allen, J. K. Wassei, K. Nelson, R. B. Kaner, and Y. Yang, “Low-Temperature Solution Processing of Graphene-Carbon Nanotube Hybrid Materials for High-Performance Transparent Conductors”, Nano Letters, Vol. 9, no. 5, pp. 1949–1955, 2009.

Disclaimer: The views expressed here are those of the interviewee and do not necessarily represent the views of Limited (T/A) AZoNetwork, the owner and operator of this website. This disclaimer forms part of the Terms and Conditions of use of this website.


Please use one of the following formats to cite this article in your essay, paper or report:

  • APA

    Banerjee, Kaustav. (2019, July 15). Carbon Nanomaterials for Designing Next-Generation Green Electronics. AZoNano. Retrieved on June 15, 2024 from

  • MLA

    Banerjee, Kaustav. "Carbon Nanomaterials for Designing Next-Generation Green Electronics". AZoNano. 15 June 2024. <>.

  • Chicago

    Banerjee, Kaustav. "Carbon Nanomaterials for Designing Next-Generation Green Electronics". AZoNano. (accessed June 15, 2024).

  • Harvard

    Banerjee, Kaustav. 2019. Carbon Nanomaterials for Designing Next-Generation Green Electronics. AZoNano, viewed 15 June 2024,

Tell Us What You Think

Do you have a review, update or anything you would like to add to this article?

Leave your feedback
Your comment type

While we only use edited and approved content for Azthena answers, it may on occasions provide incorrect responses. Please confirm any data provided with the related suppliers or authors. We do not provide medical advice, if you search for medical information you must always consult a medical professional before acting on any information provided.

Your questions, but not your email details will be shared with OpenAI and retained for 30 days in accordance with their privacy principles.

Please do not ask questions that use sensitive or confidential information.

Read the full Terms & Conditions.