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Magma Unveils Next-Gen ICs at 28-nm Process Node to Accelerate SoC Implementation

Magma® Design Automation Inc. (Nasdaq:LAVA), a provider of chip design software, today unveiled Talus® 1.2, a next-generation integrated circuit (IC) implementation solution that accelerates the design cycle of systems on chip (SoCs).

The new Talus system enables engineers to implement 1 million to 1.5 million cells per day on large designs or blocks of 2 million to 5 million cells – with crosstalk avoidance, advanced on-chip variation (AOCV) and multi-mode multi-corner (MMMC) analysis enabled. Already silicon-proven at the 40-nanometer (nm) node, Talus is currently in use for complex 28-nm designs. With these latest enhancements, Talus is primed to handle the challenges of designing at the 20-nm process node and beyond.

Talus 1.2 leverages faster, more accurate routing, timing and extraction technologies and advanced capabilities to deliver five to six times faster turnaround time, including:

  • Talus MX Router: Offers enhanced global, track and detailed routing capabilities, convergent timing through the flow, and eliminates DRC violations.
  • Talus MX Timer: Based on Magma's next-generation sign-off timing analysis technology, enables faster more accurate timing analysis.
  • Talus MX Extractor: Based on Magma's latest high-speed, multi-corner extraction technology, provides faster, more accurate extraction.
  • Concurrent MMMC optimization: Manages five times as many timing scenarios than traditional solutions, while providing a 10X runtime improvement.
  • AOCV: Ensures tight timing correlation throughout the flow.
  • Crosstalk Avoidance: Detects and corrects crosstalk violations during optimization and implementation.

"The positive results we achieved from Magma's Talus 1.2 platform reaffirmed our decision to select this tool to support our complex silicon project needs," said George Apostol, executive vice president of Engineering and Operations, and chief technical officer at Exar Corporation. "Critical to our customers, our devices must support high levels of data traffic without bottlenecks, requiring efficient routing. Talus 1.2 has solved many physical design issues and has improved place and route runtimes over prior releases, enabling us to shorten development cycles and accelerate shipping next-generation devices to customers to meet dynamic market requirements."

"Chip design teams are under constantly increasing pressure to improve productivity, even as the designs they tackle grow in size and complexity," said Premal Buch, general manager of Magma's Design Implementation Business Unit. "Economics dictate that design teams cannot expand in proportion with growing design sizes, nor can turnaround times lengthen. To improve productivity, tools must provide more capacity and faster turnaround times while enabling designers to squeeze out more performance and reduce power consumption in their SoCs. Talus 1.2 does just that. It delivers the fastest turnaround times, highest capacity, and best quality of results for the next generation of IC designs at the 28-nm process node and below."

Talus 1.2: Faster Turnaround Times, Superior Results

Key enabling technologies in Talus 1.2 include the new Talus MX timing and extraction engines based on underlying technology borrowed from Magma's next-generation sign-off timer, Tekton™, and sign-off extractor, QCP™. Used consistently throughout Talus 1.2's RTL-to-GDSII flow, these analysis engines are fast, accurate and have significantly higher capacity. They offer new features such as AOCV and MMMC analysis, ensuring tight timing correlation throughout the flow. When combined with Tekton and QCP, Talus 1.2 provides sign-off-accurate analysis during implementation, eliminating timing ECOs and resulting in faster design closure.

For implementation at 28 nm and below, it's not uncommon for designs to require the analysis of many different timing scenarios. Magma defines timing scenarios as the number of process corners multiplied by the number of timing modes. Most solutions can only handle five to eight scenarios during implementation. Talus 1.2 performs concurrent MMMC on a single machine and can manage five times more scenarios than traditional solutions, while improving runtime by 10 times.

Talus 1.2's new routing technology addresses routing challenges at 28 nm and below, where managing crosstalk in particular becomes more difficult. Fixing crosstalk too late in the flow results, in the best case, in higher cell area and elevated leakage. In the worst case, it results in a design that will not close. Talus1.2 avoids this by identifying and controlling crosstalk throughout implementation, providing a much more convergent flow with far fewer timing surprises. Unlike other approaches, Talus 1.2 delivers far shorter runtimes and more robust designs, without increasing area and leakage.

The combination of Talus 1.2's new technologies enables designers to deliver high-performance designs quickly. For example, a networking company was able to implement a 40-nm, 2-million-instance design with 10 sign-off scenarios in just 2 days with full CCS, MMMC and crosstalk analysis enabled.



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