Launch of Three-Dimensional 22-nm Gate Length Silicon Transistors in 2012

New three-dimensional transistors made from tiny indium-gallium-arsenide nanowires can help engineers design lighter laptops and more efficient, compact and faster integrated circuits.

Researchers belonging to the Harvard and Purdue universities have built this transistor using the "top-down" method. It is the first three-dimensional gate-all-around transistor. In 2012, new silicon computer chips that are to be introduced will consist of transistors that have a vertical structure. Traditional transistors have a flat design. For advancing three-dimensional transistors, materials other than silicon are required as they have limited "electron mobility."

Semiconductors that consist of elements from both the third and fifth groups in the periodic table are called as III-V materials. Indium-gallium-arsenide is a III-V material.

The “gates” in transistors allow devices to direct current flow by switching themselves on and off. Currently, the length of such gates is around 45 nm. In 2012, the new silicon-based three-dimensional transistors that are to be introduced will have 22 nm gate lengths. By 2015, researchers may develop 14 nm gate length transistors. Silicon will not support such reductions in size and high performances.

III-V materials and devices have the capability to conduct electrons faster than silicon. And III-V alloy nanowires can help develop 10 nm gate length transistors. Smaller transistors also mean new types of insulating layers. Silicon dioxide insulators are employed in traditional transistors. But when gate length goes to below 14 nm they do not perform well and "leak" electrical charge.

By using a material with higher "dielectric constant", it will be possible to address the leaking problem. Materials such as aluminum oxide and hafnium dioxide have higher dielectric constants. The researchers used the atomic layer deposition method and applied a coating of aluminum oxide. This may help engineers design thinner dielectric layers, which will consume lesser power than silicon devices.

The study findings are to be presented at the International Electron Devices Meeting in Washington, D.C.

Source: http://www.purdue.edu/

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