Cadence Tools Achieve Certification from TSMC for 10nm FinFET Process

Cadence Design Systems, Inc. today announced that its digital, signoff and custom/analog tools have achieved V1.0 Design Rule Manual (DRM) and SPICE certification from TSMC for its 10-nanometer (nm) FinFET process. Cadence and TSMC are also continuing to collaborate on the advancement of 7nm technologies and have completed tools certification and the delivery of the latest Process Design Kit (PDK) for mutual customers to initiate early design starts based on the most current version of the DRM and SPICE model.

The Cadence® custom/analog, digital and signoff tools have been validated by TSMC on high-performance reference designs, providing customers with innovative methodologies to achieve TSMC’s 7nm and 10nm process benefits of higher performance, lower power consumption, and smaller area. The certified Cadence tools include:

  • Innovus™ Implementation System: Enables increased capacity and reduced turnaround time while supporting TSMC’s 10nm design requirements, such as floorplanning, placement and routing with integrated color-/pin-access/variability-aware timing closure, and clock tree and power optimization
  • Quantus™ QRC Extraction Solution: Delivers on TSMC accuracy requirements for all 10nm modeling features and offers multi-patterning, multi-coloring and built-in 3D extraction capability
  • Tempus™ Timing Signoff Solution: Provides integrated, advanced process calculation of delay and signal integrity effects, with static timing analysis (STA) while achieving TSMC’s rigorous accuracy standards, including those at low- and ultra-low voltage operating conditions
  • Voltus™ IC Power Integrity Solution: Cell-level power integrity tool that supports comprehensive electromigration and IR-drop (EM/IR) design rules and requirements while providing full-chip system-on-chip (SoC) power signoff accuracy
  • Voltus-Fi Custom Power Integrity Solution: SPICE-level accurate tool that supports comprehensive EM/IR design rules and requirements to analyze and signoff analog, memory and custom digital IP blocks down to the transistor device level
  • Virtuoso® custom IC advanced-node platform: Provides the innovative in-design to signoff flows, integrating signoff-quality electrical and physical design checking that is highly correlated to the Cadence TSMC-certified signoff platforms
  • Spectre® simulation platform: Spectre Circuit Simulator, Spectre Accelerated Parallel Simulator (APS), and Spectre eXtensive Partitioning Simulator (XPS) deliver fast and accurate circuit simulation with full support for advanced-node device models with self-heating and reliability effects
  • Physical Verification System: Includes advanced technologies and rule decks to support design rule checks (DRC), layout versus schematic (LVS), advanced metal fill, yield-scoring, voltage-dependent checks, pattern-matching, and in-design signoff
  • Litho Electrical Analyzer: Allows layout-dependent effect- (LDE-) aware re-simulation, layout analysis, matching constraint checking, reporting on LDE contributions, and the generation of fixing guidelines from partial layout to accelerate 10nm analog design convergence

In addition to the tools certified for TSMC’s 10nm process, the Virtuoso Liberate™ Characterization Solution and the Virtuoso Variety™ Statistical Characterization Solution have been validated to deliver accurate Liberty libraries including advanced timing, noise and power models utilizing innovative new methods needed for Liberty Variation Format (LVF) models to enable process variation signoff and electromigration models for ultra-low-power applications. Libraries characterized by these two solutions were used in the 10nm v1.0 STA tool certification. Cadence and TSMC also validated a custom/mixed-signal design reference flow for the 10nm process. The flow includes the following key capabilities for improving design productivity:

  • Advanced simulation capabilities including variation analysis, EM/IR analysis and self-heating impact: Helps designers create robust, reliable and high-yield designs
  • Color-aware custom layout including rapid prototyping, automated routing and electrically and LDE-aware design: Provides a high level of automation in exploring the impact of physical effects on circuit performance
  • Virtuoso Layout Suite for Electrically Aware Design: Provides innovative in-design electromigration routing and parasitic resistor/capacitor (RC) checks that understand colored design, allowing design teams to achieve faster time to market with better circuit performance

“The certification of our tools enables systems and semiconductor companies to deliver advanced-node designs to market faster for mobile phones, tablets, application processors and high performance computing applications,” said Dr. Anirudh Devgan, senior vice president and general manager of the Digital & Signoff Group and the System & Verification Group at Cadence. “Through our deep collaboration with TSMC, we are actively working with customers on 10nm designs while also advancing the 7nm design process to enable customers to maximize the benefits of these leading-edge process nodes.”

“We worked closely with Cadence to certify its set of tools and deliver digital and custom/mixed-signal reference flows that can enable customers to reduce iterations and improve predictability when creating 7nm designs,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “This marks the production release of our 10nm technology design support.”

For more information on the Cadence tools, please visit



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