Cadence IP for TSMC 10nm FinFET Process Demonstrates 20% Power Reduction and 50% Area Reduction

Cadence Design Systems, Inc., today announced a broad intellectual property (IP) portfolio for TSMC’s 10nm FinFET (N10) process. Cadence has already secured multiple design wins with this portfolio and is actively engaged with customers as adoption of TSMC’s leading-edge process grows. The initial deliveries of Cadence IP for the N10 process demonstrate a 20 percent power reduction and 50 percent area reduction compared to TSMC’s 16nm process technology, and are ideal for mobile and network infrastructure applications.

The Cadence IP portfolio for N10 includes DDR4, USB 3.0, PCI Express® (PCIe®) 3.0, ADC, PLL and monitoring IP. For detailed product information and availability details, customers should contact their local Cadence salesperson.

“Together with TSMC, we provide innovations that lead to wider adoption of the newest technology nodes in the market,” said Hugh Durdan, vice president of marketing for Design IP at Cadence. “As a leading IP supplier, Cadence is well-positioned to enable customers working on 10nm designs to stay ahead of the competition by providing them early IP access to protocols most relevant to their markets.”

“The long-term partnership we have with Cadence enables us to work closely from the earliest phases of technology development to deliver initial IP to our customers on our latest process offerings,” said Suk Lee, senior director of the Design Infrastructure Marketing Division at TSMC.

Source: http://www.cadence.com/

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