Cadence Design Systems, Inc., today announced the Cadence® Memory Model for the LPDDR5 standard. This new verification IP (VIP) product enables engineers to verify that system-on-chip (SoC) designs are compliant with the JEDEC interface standard, and that they can operate correctly in a system with the actual memory components. Validation of designs using the LPDDR5 memory model reduces the risk of mistakes, rework and delayed production, leading to faster production ramp-up and higher product quality.
LPDDR5 is the next generation of low-power DRAM and is designed to speed performance, improve signal integrity and reduce refresh times. It is widely anticipated to be used in both mobile and server applications. Due to its enhanced performance, phones and tablets are expected to gain laptop-class performance, with datacenter servers maintaining performance but consuming much less energy.
“By continually adding to the industry’s most complete and widely used memory model portfolio, Cadence enables customers to quickly take advantage of new standards such as LPDDR5 in their designs,” said Erik Panu, corporate vice president, IP Group at Cadence. “Our customers are eager to take advantage of the performance and power benefits of LPDDR5, and the early availability of these memory models can allow them to accelerate their adoption of this new technology with confidence.”
The new Cadence memory model for LPDDR5 is available now for pre-order by early adopters, with general availability scheduled for late Q4. To learn more about this product, go to www.cadence.com/news/LPDDR5Memory.