TSMC Honors Cadence with Two Partner of the Year Awards

Cadence Design Systems, Inc. today announced that it received two TSMC Partner of the Year awards at this year’s TSMC Open Innovation Platform® (OIP) Ecosystem Forum. Cadence was presented with awards for both joint development of the 10nm FinFET design infrastructure and analog/mixed-signal IP.

The award for joint development of the 10nm design infrastructure was given based on the early, in-depth collaboration between TSMC and Cadence on FinFET enablement and the development of this latest advanced-node technology for next-generation system-on-chip (SoC) designs. Cadence provides combined digital, signoff and custom/analog tool flows that are integrated on a common OpenAccess database, incorporating integrated signoff engines that have been validated by TSMC on high-performance reference designs. Cadence® tools certified for TSMC’s 10nm process include Innovus™ Implementation System, Quantus™ QRC Extraction Solution, Tempus™ Timing Signoff Solution, Voltus™ IC Power Integrity Solution, Voltus-Fi Custom Power Integrity Solution, Virtuoso® custom IC advanced-node platform, Physical Verification System, Litho Electrical Analyzer and the entire Spectre® simulation platform. For more information on the Cadence tools, please visit www.cadence.com/products/Pages/all_products.aspx.

The analog/mixed-signal IP award was based on customer feedback, portfolio breadth, strong technical support capabilities and customer adoption/production volume. The Cadence IP portfolio is comprised of Denali® memory, interface, and analog IP and includes protocols such as DDR4, LPDDR4, ONFI 4, UFS, SATA, PCIe® 4.0, USB 3, MIPI SLIMBus, SoundWire, CSI, DSI, UniPro, DigRF 100G Ethernet, XAUI, PON, SGMII, LTE, and WiGig. For more information on Cadence IP, please visit http://ip.cadence.com.

“The award recognition from TSMC further exemplifies that Cadence IP and tools can successfully enable customers to address their power, performance and area requirements for advanced SoC designs,” said Dr. Chi-Ping Hsu, senior vice president and chief strategy officer for EDA at Cadence. “Our long-standing relationship with TSMC demonstrates our joint dedication to collaborating with customers who are at the forefront of these new process nodes.”

“We presented these awards to Cadence based on its continued ability to provide quality of results via its analog/mixed-signal IP and 10nm FinFET solutions,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “We’ve worked closely with Cadence for many years on the development of advanced, reliable solutions for our mutual customers and look forward to furthering our collaboration to stay at the forefront of design innovations.”

Source: http://www.cadence.com/

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