Plasma-Engineered TiN Cuts Switching Voltage in Ultrathin Ferroelectric Memory Capacitors

By Dr. Noopur JainReviewed by Susha Cheriyedath, M.Sc.Nov 5 2026

By changing the texture and surface chemistry of a TiN electrode, researchers tested whether a 5 nm ferroelectric capacitor could meet the voltage, speed, and endurance demands of future memory cells.

Paper: Resolving the Kay–Dunn limit and the speed–endurance dilemma in ferroelectric Hf0.5Zr0.5O2 for DRAM-class sub-volt capacitors. Image Credit: Kathrine Andi / Shutterstock

*Important notice: This news reports on an unedited version of an accepted paper and is awaiting final editing. Therefore, the paper should not be regarded as conclusive or treated as established information.

In a recent article in the journal Nature Communications, researchers showed that plasma-engineered (111)-textured TiN electrodes with nitrogen-rich, oxidation-resistant surfaces enable ultrathin ferroelectric Hf0.5Zr0.5O2 capacitors to operate at low voltage without hard electrical breakdown over 10^12 bipolar cycles.

Extrapolating the measured area dependence to DRAM-relevant footprints projects sub-ns to low-ns polarization reversal, helping to mitigate practical voltage-scaling and speed-endurance constraints for DRAM-class memory applications.

Challenges in ferroelectric scaling

Scaling DRAM technology is increasingly hindered by limitations in capacitor charge storage and energy efficiency. Conventional DRAM cells rely on a one-transistor–one-capacitor (1T–1C) design, where reducing capacitor size while maintaining sufficient sensing charge is physically challenging.

Although three-dimensional integration can increase memory density, the capacitor's footprint often dominates the cell area, so increasing effective charge density is as important as geometric scaling.

Ferroelectric hafnium zirconium oxide (Hf0.5Zr0.5O2, HZO) thin films are especially promising at the nanoscale because they remain ferroelectric even below 10 nm, are CMOS-compatible, and can be grown conformally by atomic layer deposition (ALD).

Polarization switching in these films contributes a non-volatile charge component much larger than the dielectric response alone, enabling greater charge storage capacity. But integrating such ultrathin ferroelectric films into DRAM-class capacitors demands switching speeds below 10 ns, high endurance over many cycles, and operation at low voltages near logic levels.

Plasma-engineered TiN electrode fabrication

This study used plasma engineering to improve the interface between the ferroelectric HZO layer and the bottom TiN electrode, reducing switching voltage without sacrificing switched charge, speed, or endurance.

The researchers used plasma-enhanced atomic layer deposition (PEALD) with NH3/Ar plasma chemistry to grow (111)-textured TiN electrodes with nitrogen-rich, oxidation-resistant surfaces.

Two-dimensional capacitively coupled plasma modeling showed that NH3/Ar plasmas produce a more uniform and abundant distribution of reactive nitrogen species than N2/Ar plasmas. The calculations did not directly measure radical flux to the surface or termination coverage.

Density functional theory calculations found that nitrogen-rich conditions favor N-terminated TiN-(111) surfaces and that N adsorption is more favorable on TiN-(111) than on TiN-(001); the paper notes that the N-termination fraction was not measured directly.

Experimental characterization involved X-ray diffraction, high-resolution X-ray photoelectron spectroscopy (XPS), scanning transmission electron microscopy (STEM), and energy-dispersive X-ray spectroscopy (EDS). XRD showed the stronger TiN-(111) texture, while XPS showed a lower fitted TiO2 contribution. STEM-EDS found a thinner and more uniform bottom interfacial layer in NH3/Ar-deposited electrodes than in N2/Ar counterparts.

Electrical characterization entailed measuring polarization-voltage hysteresis loops, switching kinetics, and endurance under bipolar pulse trains at room temperature using a precision parameter analyzer.

Switching kinetics were analyzed using the nucleation-limited switching (NLS) model, which characterized the distribution of local switching times. The researchers measured switching across experimentally accessible capacitor areas and extrapolated the area dependence to dimensions relevant to scaled memory cells.

Frequency-dependent measurements and transient current fitting assessed intrinsic coercive voltages, while synchrotron-based grazing-incidence wide-angle X-ray scattering (GIWAXS) tracked structural and stress changes during cycling. Compact Verilog-A models and circuit simulations examined whether the measured ferroelectric response could provide useful sensing margins in 1T–1C cell architectures.

Switching kinetics and endurance analysis

Using NH3/Ar plasma in TiN deposition produced a pronounced (111) texture with nitrogen-rich surfaces that substantially suppressed interfacial oxidation during the later growth of ultrathin 5 nm HZO films.

XPS showed that the fitted TiO2 contribution on the bare TiN-(111) electrode was about half that on TiN-(002), and STEM-EDS analyses found a thinner (0.5 ± 0.2 nm) and more uniform interfacial layer than in TiN-(002) textured electrodes grown via N2/Ar plasma, which exhibited thicker (0.7 ± 0.4 nm) and less uniform interfaces.

These interface differences coincided with lower switching voltage and a narrower distribution of switching conditions.

Devices fabricated on TiN-(111) electrodes exhibited saturated hysteresis loops at low voltages (0.6 V), with remanent polarization (2Pr) around 31.5 μC/cm² and a reduced coercive field (Ec) near 0.62 MV/cm, placing the stack among the HfO2-based capacitors with the lowest reported coercive fields while retaining a large remanent polarization.

Endurance tests showed no hard electrical breakdown through 10^12 bipolar switching cycles at 0.6–1.0 V, but the 0.6 V device reached 26.5% polarization fatigue at 10^12 cycles; using the paper's less-than-20% fatigue criterion, its endurance was 6 × 10^11 cycles. At 1.0 V, the fatigue loss at the endpoint was 18.5% at 10^12 cycles.

Direct switching measurements on 25 μm² capacitors gave t0.5 values of about 42 ns at 0.6 V and 8.1 ns at 1.0 V; NLS fits characterized the underlying distribution of local switching times, and extrapolation to a roughly (250 nm)² footprint gave sub-ns to low-ns switching across 0.6–1.0 V.

These results mitigate the external-voltage penalty associated with thickness scaling rather than overturning the Kay–Dunn relation. This means the capacitor requires less externally applied voltage while the underlying thickness-scaling behavior remains. After finite-screening correction, the thickness dependence returns to an exponent of −0.63 ± 0.03, close to −2/3.

Complementary GIWAXS measurements tracked a reproducible lattice change during wake-up, with estimated in-plane stress falling from about 1.48 to 0.63 GPa over 10²–10⁵ cycles; the changes are consistent with structural evolution and stress relaxation rather than an unchanged stress state.

Circuit-level simulations of common-plate 1T–1C memory cells, incorporating the measured ferroelectric switching characteristics, gave 482 mV short-standby and 201 mV long-standby sensing margins at 1.1 V under a 20 fF bit-line load. These are simulation results for a proposed common-plate FeRAM architecture, not a demonstration of a complete scaled DRAM array.

Implications for DRAM capacitors

This work demonstrates that plasma-engineered (111)-textured TiN electrodes with N-rich, oxidation-resistant surfaces enable reliable low-voltage switching in 5 nm Hf0.5Zr0.5O2 capacitors, reducing the external-voltage penalty associated with scaling.

The devices exhibit low coercive fields (~0.62 MV/cm) and high remanent polarization (2Pr = 31.5 μC/cm²) at sub-volt operation, with no hard electrical breakdown through 10¹² cycles; polarization fatigue varied with drive voltage.

Area- and voltage-dependent switching kinetics project sub-ns to low-ns reversal at DRAM-relevant footprints, while the voltage-matched measurements extend beyond the conventional speed-endurance trend. Interface and texture engineering offer a practical route to ferroelectric memory capacitors with low operating voltage, fast switching, and high cycle counts for high-density memory applications.