Posted in | News | Nanoelectronics

STMicroelectronics Introduces New Microprocessor Based on 55nm HCMOS Technology

STMicroelectronics (NYSE:STM) , a world leader in system-on-chip technology, today introduced the industry's first embedded microprocessor that couples two ARM Cortex-A9 cores with a DDR3 (Third-generation double-data rate) memory interface.

Manufactured in ST's low-power 55nm HCMOS (high-speed CMOS) process technology, the SPEAr1310 delivers high computing power and customizability for multiple embedded applications together with the high level of cost competitiveness offered by system-on-chip devices.

The new microprocessor combines the unrivalled low power and multi-processing capabilities of the ARM Cortex-A9 processor core with innovative Network-on-Chip (NoC) technology. The dual ARM Cortex-A9 processors support both fully symmetric and asymmetric operations, at speeds of 600MHz/core (industrial worst-case conditions) for 3000 DMIPS equivalent. NoC is a flexible communications architecture that enables multiple different traffic profiles while maximizing data throughput in the most performance- and power-efficient way.

"SPEAr1310 is the first device in the recently announced SPEAr1300 family and others will follow shortly," said Loris Valenti, General Manager of STMicroelectronics' Computer Systems Division. "With its innovative architecture and powerful feature set, SPEAr1310 is at the leading edge of the embedded processor market and enables an unprecedented mix of cost competitiveness, performance and flexibility."

Equipped with an integrated DDR2/DDR3 memory controller and a full set of connectivity peripherals, including, USB, SATA and PCIe (with integrated PHY), in addition to a Giga Ethernet MAC, ST's SPEAr1310 microprocessor targets high-performance embedded-control applications across market segments from communication and computer peripherals to industrial automation.

Cache memory coherency with hardware accelerators and I/O blocks increases throughput and simplifies software development. The Accelerator Coherency Port (ACP), coupled with the device's NoC routing capabilities, addresses the latest application requirements for hardware acceleration and I/O performance. ECC (Error Correction Coding) protection against soft and hard errors on both DRAM and L2 Cache memories dramatically improves the Mean-Time-Between-Failures for enhanced reliability.

Source: http://www.st.com/

Citations

Please use one of the following formats to cite this article in your essay, paper or report:

  • APA

    STMicroelectronics. (2019, February 13). STMicroelectronics Introduces New Microprocessor Based on 55nm HCMOS Technology. AZoNano. Retrieved on June 19, 2024 from https://www.azonano.com/news.aspx?newsID=18811.

  • MLA

    STMicroelectronics. "STMicroelectronics Introduces New Microprocessor Based on 55nm HCMOS Technology". AZoNano. 19 June 2024. <https://www.azonano.com/news.aspx?newsID=18811>.

  • Chicago

    STMicroelectronics. "STMicroelectronics Introduces New Microprocessor Based on 55nm HCMOS Technology". AZoNano. https://www.azonano.com/news.aspx?newsID=18811. (accessed June 19, 2024).

  • Harvard

    STMicroelectronics. 2019. STMicroelectronics Introduces New Microprocessor Based on 55nm HCMOS Technology. AZoNano, viewed 19 June 2024, https://www.azonano.com/news.aspx?newsID=18811.

Tell Us What You Think

Do you have a review, update or anything you would like to add to this news story?

Leave your feedback
Your comment type
Submit

While we only use edited and approved content for Azthena answers, it may on occasions provide incorrect responses. Please confirm any data provided with the related suppliers or authors. We do not provide medical advice, if you search for medical information you must always consult a medical professional before acting on any information provided.

Your questions, but not your email details will be shared with OpenAI and retained for 30 days in accordance with their privacy principles.

Please do not ask questions that use sensitive or confidential information.

Read the full Terms & Conditions.