Xradia Announce The Sale of Transmission X-Ray Microscopes to Semiconductor Manufacturers

Xradia, Inc., a developer and manufacturer of ultra-high-resolution x-ray imaging systems for 3D tomography and nanotechnology applications, today announced the sale of three of its MicroXCTTM 3D Transmission X-ray Microscopes, to semiconductor manufacturers for advanced packaging process development and failure analysis. Combining spatial resolution below 1.5µm and feature recognition of 500nm, with full 3D tomography capability, the MicroXCTTM is ideally suited to the engineering and failure analysis of next-generation semiconductor packages, including multi stacked die and flip-chip architectures. Two of the systems are being deployed to fabs in the US for advanced package development and the third is headed to Asia where it will be used to examine ball grid arrays.

“These system sales validate the importance of high-resolution x-ray tomography as a critical new analytical tool for semiconductor manufacturing,” said Dr. Wenbing Yun, founder and President of Xradia. “3D x-ray microscopy enables the non-destructive investigation of design features or process defects, thereby lowering development costs and speeding time to market, “said Yun. “The ROI of Xradia’s new x-ray microscope system was evident from the very first sample images,” said My Nguyen, senior researcher at Altera Corporation, one of the new system customers. “We are able to image features of interest not otherwise observable with other techniques. No sample prep means enormous cost savings and fast turn around time,” said Nguyen.

High resolution 3D x-ray tomography provides critical new imaging capability for semiconductor packaging, including C4 ball grid arrays, stacked die, solder bumps and packaging interconnects. Defects such as solder non-wet, cracks, voids, delamination, opens and shorts are readily imaged. New applications are also emerging for RoHS lead-free development and vias in ceramic packaging. Xradia also manufactures microscope systems with sub 50nm resolution for chip and die-level applications.

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