Industry Leaders to Share Strategies to Advance State of the Art in Interconnect Metallization Technology

While seeking "faster, cheaper, smaller" devices through continued scaling, chipmakers are also looking to new three-dimensional methods to achieve greater performance and functionality. Whether scaling down in two dimensions or scaling vertically in the third, key challenges remain, from finding the right low k solution and controlling resistance scaling in advanced interconnects to deciding which of the many TSV process flows will emerge as the industry’s standard.

On June 1st, at a forum hosted by Applied Materials, a panel of industry thought leaders will share their strategies to advance the state of the art in interconnect metallization technology. The program will be led by Dr. Hans Stork, chief technology officer of Applied’s Silicon Systems Group, and feature speakers from IMEC, Samsung, Semitool and Toshiba. This important event will take place in conjunction with the prestigious IEEE International Interconnect Technology Conference (IITC), which is being held this year in Sapporo, Japan.

Title: “Multiple Dimensions of Metallization – from Interconnect to 3D Integration

Where: Royton Sapporo Hotel , Hokkaido, Japan

When: Monday, June 1st, 2009

Schedule: 5:30pm Registration and Reception
6:00pm Seminar program
7:00pm Panel Discussion

To register:

Applied Materials, Inc. (Nasdaq:AMAT) is the global leader in Nanomanufacturing Technology™ solutions with a broad portfolio of innovative equipment, service and software products for the fabrication of semiconductor chips, flat panel displays, solar photovoltaic cells, flexible electronics and energy efficient glass. At Applied Materials, we apply Nanomanufacturing Technology to improve the way people live.

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