Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics, today announced that the Chinese Academy of Sciences Institute of Computing Technology (ICT) has adopted the Cadence® Incisive® Xtreme® III System for accelerating the development of RTL design with a verification flow for its next-generation 64 million-plus gates Loongson III advanced multi-core microprocessor.
The deployment of the Incisive Xtreme III System for developing the ICT's advanced 65- and 45-nanometer multi-core processor enabled ICT engineers to accelerate system-level verification while validating software operations. The Xtreme III System supported the ICT's goals of accelerating hardware/software development while reducing the risk of costly re-spins.
"The Xtreme III System has made a significant impact in accelerating our simulation runtime process by a factor of 860 times, and has made co-verification a predictable process for our next-generation Loongson III multi-core design," said Dr. Weiwu Hu, chief architect of the ICT's CPU division. "This Cadence technology has helped us improve overall productivity, predictability and quality of our Loongson III development."
Using Xtreme III, the ICT was able to accelerate simulation productivity and to find at least 10 critical system-level bugs that could only be exposed by running several billions of cycles in a system-level environment. The system enabled early access to a flexible, high-performance verification platform for hardware/software co-development and delivered powerful built-in productivity features such as hot-swap and VCD-on-Demand. These capabilities enabled ICT developers to quickly bring up the system and find system-level bugs more simply than through traditional debugging methods.
The ICT also used Xtreme III to augment their FPGA prototyping flow to thoroughly address the complexity of their next-generation multi-core microprocessors. Xtreme III fully automates compiling and partitioning, virtually eliminating pin limitations and timing issues commonly found in large-scale FPGA prototyping systems. The accelerated scalable verification flow provided by Xtreme III gave ICT engineers the required verification throughputs and ease of use while minimizing the effort required in debugging the design in a system-level environment.
"The ICT's experience with its Loongson III design is a perfect example of the great value hardware-based solutions like the Incisive Xtreme III System can deliver to companies seeking greater productivity, predictability and quality," said James Liu, Cadence general manager of China and Hong Kong.
The Cadence Incisive Xtreme series of high-performance, high-capacity accelerators/emulators speeds the functional verification of designs at the behavioral, RTL, and gate levels. Designed for multi-user, multi-site, multi-purpose systems, the Xtreme series integrates with the Incisive simulation environment to perform advanced verification planning and to drive coverage-based, metric-driven verification closure.