Posted in | Nanoelectronics

TSMC Leverages Cadence’s Technologies to Design Complex Nanometer Chips

Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, today announced that transaction-level modeling (TLM)-driven design and verification, 3D-IC implementation and integrated DFM are among the many cutting-edge Cadence® technologies and flows that have been incorporated into TSMC Reference Flow 11.0.

The Cadence contributions aid in the design, implementation, verification and signoff of complex 28-nanometer chips from TLM through GDSII. Supporting the EDA360 vision, these additions to the TSMC flow help the two companies’ mutual customers reduce the design cycle for implementing complex high-performance, low-power, mixed-signal chips. Cadence support for the new reference flow marks the company’s latest step in delivering key elements of the EDA360 vision.

“Cadence and TSMC have worked together to reduce development costs for our mutual customers by helping them migrate to a higher-level of abstraction and advanced process nodes,” said ST Juang, senior director of Design Infrastructure Marketing at TSMC. “With the addition of Cadence tools and solutions, TSMC Reference Flow 11.0 comprehensively addresses vital design concerns and increases design productivity by enabling ESL design and verification and 3D-IC integration to become part of the mainstream flow.”

The EDA360 vision calls for a collaborative ecosystem that enables System to Silicon Realization. The Cadence contributions to the TSMC Reference Flow can help customers achieve those goals faster and more cost-effectively through the fast creation, reuse and integration of large digital, analog, and mixed-signal IP blocks.

Comprehensive TLM-Driven design and verification and 3D-IC Design Solutions

TSMC’s new reference flow leverages the capabilities of leading Cadence TLM-driven design and verification technologies and methodology. Complete TLM-to-GDSII design is enabled by raising the level of design abstraction from RTL to TLM, and through the methodology deployment of Cadence high-level synthesis, early power trade-offs and optimization, and metric-driven functional verification. Advanced 3D design capabilities include physical design and implementation; RC extraction; analysis of timing, signal integrity, IR drop, electromagnetic and thermal analysis; and physical verification.

Customers can benefit by migrating to a higher level of abstraction because it increases their design and verification productivity for new IP creation and reuse from system-level design to physical implementation. Unique Cadence engineering change order (ECO) capabilities help eliminate unnecessary iterations for faster time to market. The 3D-IC design capabilities improve implementation decisions for ensuring optimal performance and power tradeoffs in packaging. With design-for-manufacturability solutions integrated into implementation tools, designers can safely complete their block- or chip-level designs to meet time-to-volume targets.

New Capabilities for Low-Power, Advanced-Node and Mixed-Signal Design

Cadence also has worked with TSMC to bring additional support for low-power, advanced-node and mixed-signal designs. In the area of low power, enabled by the Common Power Format (CPF), the flow now supports power state validation and IP library view support. Advanced node support now includes litho hot-spot fixing using iLPC and dummy metal/via insertion with stand-alone GDS utility in automatic place and route tool. For system-in-package (SiP) mixed-signal designs, there is packaging support with SiP die/package floorplanning, mixed-signal IR drop and advanced SiP static timing analysis. These new reference flow elements offer design teams greater visibility and predictability from system level through signoff; help optimize tradeoffs in power, performance and area; and aid in maximizing the potential yield.

“Our customers are looking to improve their productivity in order to keep up with increasing design complexity and to meet tight time-to-market requirements,” said Charlie Huang, senior vice president and chief strategy officer at Cadence. "With the new reference flow, Cadence and TSMC have delivered significant technology innovations and methodologies to help enable a complete and predictable System to Silicon Realization flow.”



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