The SOI Industry Consortium, Soitec and CEA-Leti have jointly organized the sixth annual workshop on fully depleted silicon-on-insulator (FD-SOI) technology for sophisticated semiconductor architectures.
The event will be held at the Marriott Marquis Hotel in San Francisco, California on February 24, 2012. The forum will provide the latest data on utilizing FD-SOI wafers to create power-efficient integrated circuits needed for mobile and consumer electronics applications. The event will be held a day after the IEEE International Solid-State Circuits Conference, which will also be held at the same venue.
The FD-SOI workshop will include presentations by academia as well as experts from the semiconductor industry. Presentations topics include the Recent Advances in FD-SOI; Strain Options for FD-SOI; Advanced FD-SOI Design; Planar Fully Depleted Silicon Technology to Design Competitive SOCs at 28 nm and Beyond: Design Issues; Library and Physical IP Porting for FD-SOI; Planar Fully Depleted Silicon Technology to Design Competitive SOCs at 28 nm and Beyond: Technology Issues; 20 nm FD-SOI Models; Enabling Substrate Technology for a Large-Volume Fully Depleted Standard; and FinFET on SOI.
FinFETs based on planar FD-SOI and SOI technologies are serious competitors for high-performance, low-power architectures. FD-SOI technology facilitates in developing cost-effective, low-power CMOS devices for the mobile and consumer electronics markets. Completely depleted transistors achieve the desired circuit speed for data-processing yet at the same time use minimum power, which is important in tablets and smart phones.
SOI Industry Consortium’s Executive Director, Dr. Horacio Mendez stated that the workshop provides the latest advancements in the FD ecosystem. Each year, the event is graced by key decision makers and industry experts as SOI applications continue to achieve significance in high-volume markets.