Soitec, a provider of semiconductor materials for the energy and electronics markets, has outlined its fully depleted (FD) product roadmap consisting of two products intended for advanced planar and three-dimensional (FinFET) transistors.
Soitec's FD wafers have pre-integrated key features of transistors in the wafer structures themselves. They enable an early, low-risk shift at the 28 nm node to 10 nm and beyond, while reducing costs and improving power efficiency and performance of mobile devices. The company will also work on improving the performance of transistors made of silicon as well as other new materials. Through internal and joint research and development programs, the company also expects the migration from 300 to 450 mm wafers for supporting the industry roadmap. Both the FD-2D and FD-3D wafers are completely scalable to 450 mm.
Soitec's products support the FD International Technology Roadmap for Semiconductors of the industry by accelerating market-reach time and reducing over production costs of chipmakers. The company’s FD-2D product series facilitates an innovative planar method to FD silicon technology at 28 nm node where chipmakers can continuously get benefits from their existing process technologies and designs.
The FD-2D wafer has an ultra-homogenous and ultra-thin silicon layer as its top layer, enabling it to attain planar FD transistors with silicon of thickness down to 5 nm under the gate. An ultra-thin buried oxide (BOX) layer with a thickness of 25 nm is sandwiched between the silicon base and the top silicon layer. Future generations can take advantage from even thinner BOX layers having a thickness of down to 10 nm, paving the way for down to 14 nm planar transistor scalability for mobile devices.
Soitec's FD-3D product series enables three-dimensional (FinFET) architectures, while lowering investment and time and simplifying the transistor manufacturing process at less than 20 nm. The FD-3D wafer has a silicon top layer whose thickness varies with the requirements of customers. The fin height is predefined by this top layer placed over a BOX layer, which offers built-in intrinsic separation. It simplifies the FinFET production process, reduces capital and operating costs, and increases production throughput. These advantages result in fewer industrialization challenges, shorter process development learning cycles, and faster market-reach time for FinFET technology in the mainstream foundry market.