GLOBALFOUNDRIES plans to display an improved silicon-validated design flow for the company’s 28 nm super low power (SLP) Gate First High-k Metal Gate process technology at the Design Automation Conference to be held in San Francisco, California.
The design flow offers a full front-to-back support for sophisticated analog/mixed-signal (AMS) design utilizing the most recent design automation technology of the industry. Moreover, GLOBALFOUNDRIES will demonstrate design flows that have been jointly developed with its EDA collaborators in qualifying analog and digital ‘double patterning aware’ flows for GLOBALFOUNDRIES’ 20 nm process node, with silicon validation at this node anticipated in the beginning of 2013.
GLOBALFOUNDRIES’ new mixed vendor flow is compatible with multiple vendor tools such as Cadence Design Systems’ Virtuoso technology for layout; Mentor Graphics tool for physical verification; and Cadence and Synopsys tools for parasitic extraction. The flow is completely silicon validated for functionality between 300 MHz and up to 3 GHz. Silicon validation comprised of peak-to-peak period jitter, clock duty cycle and operating current for critical analog blocks. The flow supports GLOBALFOUNDRIES' DRC+, a silicon-validated solution. GLOBALFOUNDRIES supports and maintains the flows, which are completely incorporated with the PDK.
The GLOBALFOUNDRIES 28 nm AMS production flow fully backs a digital implementation module relied on the Cadence’s Encounter Digital Implementation System. Moreover, the truly integrated mixed-signal flow also features extraction support and inductor synthesis from EDA suppliers, which include Integrand Software, Helic and Lorentz Solutions. The flow also supports for EM/IR analysis utilizing Apache Design’s Totem software platform and fast variation-aware analysis utilizing Solido Design Automation’s Variation Designer platform. Mentor Graphics’ Calibre tool suite provides a DRC waiver flow.
GLOBALFOUNDRIES has designed two completely implementable 20nm RTL2GDSII flows for the 20 nm process node. One is based on the Synopsys Galaxy tool suite and other one is on the basis of the Cadence Encounter platform. Both flows are under silicon validation and this validation is being done by developing an intricate double patterned test chip. The flows support physical verification, parasitic extraction, color aware place-and-route and synthesis.
Source: http://www.globalfoundries.com
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