TSMC Certifies Cadence Digital, Custom/Analog and Signoff Tools for V0.9 10nm Process

Cadence Design Systems, Inc. today announced that its digital, custom/analog and signoff tools have achieved certification from TSMC for V0.9 of its 10nm process and are currently on track to achieve V1.0 completion by Q4 2015. The certification enables systems and semiconductor companies to deliver advanced-node designs to market faster for mobile phones, tablets, application processors and high-end servers.

Highlights:

  • Cadence tools validated by TSMC on high-performance reference designs in order to enable customers to reduce iterations and improve predictability
  • Cadence and TSMC collaborate on delivering new capabilities for 10nm custom design reference flow

The Cadence® custom/analog and digital implementation and signoff tools have been validated by TSMC on high-performance reference designs in order to provide customers with the fastest path to design closure. The Cadence tools in the flow include:

  • Innovus™ Implementation System: The solution incorporates a massively parallel architecture that enables increased capacity and a reduced turnaround time. It supports all of the TSMC 10nm design requirements, such as floorplanning, placement and routing with integrated color-/pin-access /variability-aware timing closure, and clock tree and power optimization.
  • Quantus™ QRC Extraction Solution: This signoff extraction solution supports both cell-level and transistor-level extractions during design implementation and signoff using one unified foundry-certified techfile. It meets TSMC accuracy requirements for all 10nm modeling features, including multi-patterning, multi-coloring, and built-in 3D extraction capability, and produces the smallest netlist to expedite simulation runtimes.
  • Tempus™ Timing Signoff Solution: This solution offers integrated, advanced process delay calculation and static timing analysis (STA) that meets TSMC’s rigorous accuracy standards for the 10nm process. Massive parallelism in computation coupled with “in-design” signoff engineering change orders (ECOs) in the Innovus Implementation System rapidly address signoff closure to minimize ECO iteration time.
  • Voltus™ IC Power Integrity Solution: This SoC power signoff tool is certified for its accuracy in supporting comprehensive electromigration and IR-drop (EM/IR) design rules and requirements for the TSMC 10nm process. Together with other Cadence products in the flow, Voltus IC Power Integrity Solution provides a gate-level total power integrity analysis and optimization solution that helps customers to achieve the best power, performance and area (PPA), along with a fast path to design closure.
  • Voltus-Fi Custom Power Integrity Solution: This SPICE-level accurate, transistor-level tool is used to analyze and signoff analog, memory and custom digital IP blocks, and create accurate macro models that represent the power grid view of the IP blocks during the SoC power signoff run with Voltus IC Power Integrity Solution. It is certified by TSMC for its accuracy in supporting comprehensive EM/IR design rules and requirements for the 10nm process down to the transistor device level.
  • Virtuoso® custom IC advanced-node platform: This custom design platform provides the innovative “in-design to signoff” flows, integrating signoff-quality electrical and physical design checking that is highly correlated to the Cadence TSMC-certified signoff platforms. Customers experience fewer iterations in all design verification categories, which translates directly into increased designer productivity.
  • Spectre® simulation platform: Spectre Circuit Simulator, Spectre Accelerated Parallel Simulator (APS), and Spectre eXtensive Partitioning Simulator (XPS) deliver fast and accurate circuit simulation with full support for 10nm device models with self-heating and reliability effects.
  • Physical Verification System: PVS includes advanced technologies such as pattern matching, interactive DRC and in-design signoff using the Virtuoso custom IC platform and the Innovus Implementation System to significantly reduce iterations and achieve faster design closure.
  • Litho Electrical Analyzer: The TSMC API integration with Litho Electrical Analyzer allows layout-dependent effects- (LDE-) aware resimulation, layout analysis, matching constraint checking, reporting on LDE contributions, and the generation of fixing guidelines from partial layout to accelerate 10nm analog design convergence in the Virtuoso custom IC advanced-node platform.

For more information on the Cadence tools, please visit http://www.cadence.com/products/Pages/all_products.aspx.

Cadence and TSMC also worked closely on the delivery of a 10nm custom design reference flow (CDRF). The CDRF includes the following:

  • TSMC API integration that speeds up statistical simulation flows
  • New layout automation capabilities for better managing LDE
  • Robust capabilities for designing correct-by-construction FinFET arrays to avoid density gradient effects
  • New patterning methods and functionality for handling today’s sophisticated multi-patterning design styles
  • Support for extracting and analyzing real-time parasitics and EM violations during design implementation

“Through our deep collaboration with TSMC, we continue to focus heavily on advancing new innovations in the systems and semiconductor industries, enabling customers to confidently deliver advanced-node designs to the market,” said Dr. Chi-Ping Hsu, senior vice president and chief strategy officer for EDA at Cadence. “We are now actively working with customers on 10nm designs and seeing great successes that ensure our customers can stay in front of the competition.”

“We’ve continued to deepen our collaboration with Cadence to certify the Cadence toolset on the TSMC 10nm technology,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “The reference flows in both digital and custom design can help customers reduce iterations and improve predictability while bringing their products to the market.”

In related news, please see the Cadence press release titled, “TSMC Certifies Cadence Innovus Implementation System on 10nm FinFET Process,” at http://www.cadence.com/cadence/newsroom/press_releases/Pages/pr.aspx?xml=091615_tsmcinnovus.

Source: http://www.cadence.com/

Citations

Please use one of the following formats to cite this article in your essay, paper or report:

  • APA

    Cadence Design Systems. (2019, February 11). TSMC Certifies Cadence Digital, Custom/Analog and Signoff Tools for V0.9 10nm Process. AZoNano. Retrieved on October 27, 2020 from https://www.azonano.com/news.aspx?newsID=33723.

  • MLA

    Cadence Design Systems. "TSMC Certifies Cadence Digital, Custom/Analog and Signoff Tools for V0.9 10nm Process". AZoNano. 27 October 2020. <https://www.azonano.com/news.aspx?newsID=33723>.

  • Chicago

    Cadence Design Systems. "TSMC Certifies Cadence Digital, Custom/Analog and Signoff Tools for V0.9 10nm Process". AZoNano. https://www.azonano.com/news.aspx?newsID=33723. (accessed October 27, 2020).

  • Harvard

    Cadence Design Systems. 2019. TSMC Certifies Cadence Digital, Custom/Analog and Signoff Tools for V0.9 10nm Process. AZoNano, viewed 27 October 2020, https://www.azonano.com/news.aspx?newsID=33723.

Tell Us What You Think

Do you have a review, update or anything you would like to add to this news story?

Leave your feedback
Submit