Virage Logic Qualifies AEON NVM Solution on TSMC's 65-nanometer LP Process

Virage Logic Corporation (NASDAQ:VIRL), a leading provider of semiconductor intellectual property (IP) for the design of complex integrated circuits, today announced it has qualified its AEON® non-volatile memory (NVM) solution on TSMC's 65-nanometer (nm) Low Power (LP) process. As the industry's first multi-time programmable (MTP) logic NVM solution that is commercially available on a 65nm process, AEON further extends Virage Logic's NVM provider leadership position.

AEON enables IC manufacturers to embed NVM at advanced logic processes—something that was previously limited to the use of one-time programmable fuse technology—and design a truly multi-programmable product with greater flexibility and higher performance. Eliminating external EEPROM from system designs allows companies to reduce power, area and cost and increase security. AEON also enables product differentiation by enabling features such as in-field customization, calibration, encryption keys and non-volatile counters.

“AEON brings true multi-time NVM programmability to market segments where advanced-process adoption is crucial, such as security and wireless,” said Dr. Yankin Tanurhan, vice president and general manager, NVM Solutions, Virage Logic. “AEON can replace one-time programmable solutions with a fully electrically testable NVM block. And because we've built reliability into the architecture and fully qualified it on TSMC's 65nm LP process, AEON provides a low-risk, highly profitable investment.”

“TSMC supports Virage Logic's efforts to offer embedded NVM solutions at advanced process nodes because of their proven commitment to quality and reliability,” said TSMC's Dan Kochpatcharin, deputy director of IP Portfolio Marketing. “The AEON product line enables our customers to take advantage of the benefits multiple-time programmable NVM can deliver in thoroughly tested and production proven IP.”

The design of Virage Logic's AEON NVM is based on a standard logic CMOS process with no additional masks or processes required. This eliminates costly manufacturing steps normally involved with floating gate memory, while reducing the engineering effort and associated costs of integrating NVM into system-on-chip (SoC) designs.

Virage Logic rigorously qualifies AEON, subjecting it to full characterization and reliability testing over extended temperatures and manufacturing process conditions. Designed from the ground up for ultra-high yield and reliability, AEON on the 65nm LP process provides full read and program operation across a wide temperature range, from -40°C to 125°C, with minimum 10-year data retention at 125°C. On high voltage process nodes, such as 250 and 180nm, AEON provides full read and program operation ranging from -40°C to 150°C and with minimum 10-year data retention at 150°C. AEON is ideally suited for applications that require reliability even in the most demanding environments.

AEON supports 100,000 write-erase cycles and bit counts from eight bits to 8K bits. The AEON product line enables 100-percent electrical testing at wafer sort and eliminates costly field programming failures associated with one-time programmable solutions. Optimized to enable considerable manufacturing and operational flexibility, final calibration can be performed at wafer test, post-packaging or in the field. In addition, identical ICs can be calibrated and configured to implement different features at final test immediately prior to shipping.

Building on the success at mature nodes ranging from 250nm to 90nm, the AEON product line has been fully developed and qualified on TSMC's 65nm LP Logic CMOS process with 2.5V IO option. Silicon testing includes complete characterization across process splits as well as comprehensive industry standard qualification. Full characterization and qualification data is available for qualified customers upon request.


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