Xilinx Inc. and TSMC announced that they are teaming together to create the fastest time-to-market and highest performance FPGAs to be built on TSMC’s 16-nanometer FinFET i16FinFETj process, a program Xilinx calls ‘FinFast.’
The two companies are providing dedicated resources as part of a ‘one-team’ approach, and will work together to co-optimize the FinFET process with Xilinx’s UltraScale™ architecture. The program will deliver 16FinFET test chips later in 2013 and first product in 2014.
The companies are also engaged in leveraging TSMC’s CoWoS 3D IC manufacturing flow for the highest levels of 3D IC systems integration and system-level performance. Products from this collaboration will be announced at a later date.
“I am extremely confident that our ‘FinFast’ collaboration with TSMC on 16-nanometer will bring the same leadership results that we enjoyed at previous advanced technologies,” said Moshe Gavrielov, President and CEO of Xilinx. “We are committed to TSMC as the clear foundry leader in every dimension, from process technology to design enablement, service, support, quality, and delivery.”
“We are committed to working with Xilinx to bring the industry’s highest performance and highest integration programmable devices quickly to market,” said Morris Chang, TSMC Chairman and CEO. “Together we will deliver world-class products on TSMC’s 20SoC technology in 2013 and on 16FinFET technology in 2014.”
TSMC recently announced that it is accelerating the production schedule of its 16FinFET process to 2013. The Xilinx/TSMC collaboration will take full advantage of this accelerated schedule and the aggressive performance and power savings of TSMC’s 16FinFET technology.
Xilinx has worked with TSMC to infuse high-end FPGA requirements into the FinFET development process, just as it did in the development of 28HPL and 20SoC processes. To gain optimal results, further co-optimizations will be done across TSMC’s process technology and Xilinx’s UltraScale architecture and next-generation tools. UltraScale is Xilinx’s new ASIC-class architecture, developed to scale from 20-nanometer planar, through 16-nanometer and beyond FinFET technologies, and from monolithic through 3D ICs.
Source: http://www.tsmc.com/