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Synopsys Develops 28-nm Design Solutions for TSMC Reference Flow 12.0

Synopsys declared that it has come up with a complete design package for TSMC’s 28-nm process technology and advanced system-level prototyping solution. The new solution called TSMC reference Flow 12.0 comes with advanced features such as high-level synthesis and virtual prototyping linked to TSMC’s processes, extended manufacturing compliance abilities and complete support of TSMC’s design rules for the latest 28-nm system.

The Virtual Prototyping and Synphony C compiler from Synopsis provide the Reference flow 12.0 with the ability to develop and verify software and hardware platforms. Virtual prototypes are created and interconnected using the virtual prototype tool along with the open transaction-level-modelling (TLM)-2.0 from Synopsys.

The system-level flow joins the RTL and the SystemC TLM 2.0 models in VCS- based verification system with the help of hybrid virtual prototypes and UVM methodology. The Synphony C compiler has been customised to match TSMC’s processes technologies so that designers are able to attain at power-optimised results by utilizing complex C/C++ codes. The flow features a reference virtual prototype that is based on ARM Cortex-A9 MPCore fast-model type. The prototype comes with fully documented design examples for the Synphony C Compiler. The Reference Flow 12.0 comes along with a leakage optimization engine for the IC compiler. The compiler’s built-in validation engine helps in quick detection and automatic repair of the limiting layout patterns.

Some of the tools that the Reference Flow 12.0 comes along with are DesignWare IP and Verification IP and automated assembly of the IP. For verification purposes, CustomSIM for circuit simulation and MVRC for low power static checking are provided. To help in the physical implementation, IC compiler and Validator are included For ease of analysis and sign-off, we have tools such as PrimeTime, StarRC and PrimeYield. Tools like DFTMAX, TetraMAX and power compiler help in RTL synthesis and testing. Finally, for rapid yield purposes we have tools like the Yield Explorer.

Source: http://www.synopsys.com/

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