ATopTech Includes Place and Route Solution in TSMC's 20 nm Reference Flow

ATopTech, the leader in next generation physical design solutions, today announced that Aprisa™ and ApogeeTM, the company’s place and route solution, are included in TSMC’S 20nm Reference Flow.

TSMC’S 20nm process technology delivers better performance and lower power consumption than previous generations. TSMC and ATopTech collaborated in incorporating ATopTech tools in the 20nm Reference Flow to address the increasing design challenges for 20nm.

Many new technologies have been developed in Aprisa and Apogee to enable customer design successes at 20nm:

  • Double patterning technology (DPT) routing rule support
  • Color-aware routing
  • Hierarchical design flow for DPT routing
  • Vt-min width compliance
  • GDS voltage marker for spacing check
  • TCD/ICOVL insertion
  • Boundary cell insertion

“ATopTech's P&R technology is architected specifically for advanced technology design,” said Jue-Hsien Chern, CEO of ATopTech. “We have worked closely with TSMC to develop enhancements to ensure the highest possible routability for optimal manufacturing for 20nm designs. The adoption from TSMC’s 20nm Reference Flow continues our mission to provide customers with best in class physical design tools for advanced processes.”

“We are pleased to include ATopTech’s Aprisa P&R tool into the TSMC 20nm Reference Flow,” said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division. “The close collaboration between ATopTech and TSMC will help enable successful 20nm projects for our joint customers.”


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