Synopsys Offers Broad Portfolio of DesignWare PHY IP for TSMC's 16nm FinFET Plus Processes

Synopsys, Inc. today announced the availability of a broad portfolio of DesignWare® PHY IP for TSMC's 16-nanometer (nm) FinFET Plus (16FF+) processes, enabling designers to integrate required functionality in mobile and enterprise system-on-chips (SoCs) with less risk.

The silicon success of the DesignWare IP in TSMC's 16FF+GL and 16FF+LL processes enables designers to accelerate the development of SoCs that incorporate embedded memories and interface IP for USB 3.0, 2.0 and HSIC; PCI Express® 4.0, 3.0 and 2.0; SATA 6G; HDMI 2.0; MIPI D-PHY; DDR4/3 and LPDDR4/3/2 protocols on TSMC 16FF+ processes.

Silicon-proven DesignWare PHY IP, designed for high quality and reliability, offers excellent performance margins on TSMC 16FF+ processes.

Highlights:

  • DesignWare Interface PHY IP portfolio for TSMC 16FF+ processes includes USB 3.0, 2.0 and HSIC; 16G PHY; PCI Express 4.0, 3.0 and 2.0; SATA 6G; HDMI 2.0; MIPI D-PHY; DDR4 and LPDDR4/3/2 IP
  • DesignWare Embedded Memories for the TSMC 16FF+ processes include high-speed, high-density and ultra high-density SRAM, Register File and ViaROM memory compilers
  • DesignWare STAR Memory System is optimized to provide high test coverage and efficient repair of FinFET-based memories

"TSMC's long history of collaboration with Synopsys has provided designers with silicon-proven IP on advanced processes to speed development of SoCs for mobile and enterprise applications," said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division. "The availability of DesignWare IP for TSMC's 16FF+ processes enables designers to benefit from the technology's performance, power and area while accelerating their time-to-volume production."

The DesignWare STAR Memory System® product is a comprehensive, integrated test, repair and diagnostics solution that supports Synopsys and third-party embedded memories. TSMC uses DesignWare STAR Memory System to characterize all of its 16FF+ memory compilers. The optimized test and repair algorithms maximize test coverage while reducing test time, lowering test cost and improving manufacturing yield. Synopsys also provides DesignWare Logic Libraries for the TSMC 16FF+ processes that include 7.5-, 9- and 10.5-track libraries, power optimization kits and High Performance Core (HPC) kits. All Synopsys embedded memories and logic libraries, including those on TSMC 16FF+ processes, work seamlessly with the IC Compiler™ II place-and-route system that accelerates throughput and improves quality of results.

"As the leading provider of physical IP for FinFET processes, Synopsys continues to invest in IP that helps designers take full advantage of the latest processes' speed and power characteristics while implementing high-quality, proven IP in their SoCs," said John Koeter, vice president of marketing for IP and prototyping at Synopsys. "Our close collaboration with TSMC mitigates risk for designers integrating interface, embedded memory and logic library IP into high-performance, low-power SoCs using TSMC's 16FF+ process."

Availability

The DesignWare USB 3.0 and 2.0, 16G PHY, PCI Express 4.0, 3.0 and 2.0, SATA 6G, HDMI 2.0, MIPI D-PHY, DDR4 multiPHY (including DDR4/3 and LPDDR4/3/2), logic library and embedded memory IP for TSMC's 16FF+ process, as well as STAR Memory System and IC Compiler II, are available now.

About DesignWare IP

Synopsys is a leading provider of high-quality, silicon-proven IP solutions for SoC designs. The broad DesignWare IP portfolio includes logic libraries, embedded memories, embedded test, analog IP, complete interface IP solutions consisting of controller, PHY and next-generation verification IP, embedded processors and subsystems. To accelerate prototyping, software development and integration of IP into SoCs, Synopsys' IP Accelerated initiative offers IP prototyping kits, IP software development kits and IP subsystems. Synopsys' extensive investment in IP quality, comprehensive technical support and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market. For more information on DesignWare IP, visit http://www.synopsys.com/designware.

Source: http://www.synopsys.com/

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