Synopsys, Inc. (NASDAQ:SNPS) , a world leader in software and IP for semiconductor design and manufacturing, today announced the introduction of breakthrough Composite Current Source (CCS) base curve modeling technology that reduces digital cell library file size by up to 75 percent while improving application tool runtime and capacity. Starting at 65-nanometers (nm), and becoming critical at 45-nanometers, increased process variation and low power design flows, such as multi-voltage design, require more library corners as well as more complete and accurate power modeling views, causing library file size to increase ten-fold over the previous node. This is presenting a major storage, distribution and EDA tool efficiency challenge for the semiconductor industry.
"Current source modeling is an essential library requirement at 65-nanometers and below process technologies," said Noboru Yokota, general manager, Technology Development Division, Common IP & Technology Development Unit, Fujitsu Microelectronics Ltd. "However, the increase in the number of corners and the library file size can cause a major bottleneck in library deployment and EDA tool efficiency. The enhanced CCS with base curve modeling technology is designed to deliver the smallest, most efficient libraries while maintaining the high accuracy necessary at the latest process geometry nodes."
Base curve technology is an innovative new approach that takes advantage of similarities in timing and power current waveforms across various grid points as well as various cells in the libraries to minimize the amount of data stored without any impact on accuracy. Besides helping reduce library file size by a factor of four, base curve technology improves application tool capacity and allows signoff tools such as the PrimeTime(R) solution to run up to 60 percent faster. The enhanced CCS library format with base curve syntax has been approved by the Liberty(TM) Technical Advisory Board (TAB), a program of the IEEE Industry Standards and Technology Organization (IEEE-ISTO), and is available for immediate download at http://www.opensourceliberty.org/.
"It's great to see the Liberty TAB members collaborating to address real world challenges facing the semiconductor industry at the latest 45-nanometer process technology node," said Peter Lefkin, chief operating officer of the IEEE-ISTO. "The fast pace of innovation in the Liberty library modeling standard will help the industry coalesce around a single standard to improve tool interoperability and speed design flows, offering tremendous benefits to the EDA user community."