Nanoelectronics News

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New NAG Library for SMP and Multicore Now Available for Download

Nanotechnology engineers seeking better use of the processing power of multicore computer systems in addition to an easy way to migrate existing applications to multi processor architectures, can now download the new NAG Library for SMP and Multicore from Numerical Algorithms Group (NAG).

15 Apr 2010

Virage Logic’s SiWare Technologies Support TSMC’s 28nm HP Process

Virage Logic Corporation, the semiconductor industry's trusted IP partner, extends its leadership position by announcing a full suite of 28-nanometer (nm) memory compilers and logic libraries on TSMC’s High-K Metal Gate (28nm HP) process.

From TSMC Taiwan Semiconductor Manufacturing Company 15 Apr 2010

U-M Computer Engineer Develops Memristor Device That Learns and Recognizes

A cat can recognize a face faster and more efficiently than a supercomputer. That's one reason a feline brain is the model for a biologically-inspired computer project involving the University of Michigan. U-M ...

15 Apr 2010

Applied Materials Offers Advanced Technology for Flexible Touch Panel Production

Applied Materials, Inc. reports that its flat panel display (FPD) and roll-to-roll coating systems are providing the advanced technology to enable more cost-efficient and scalable touch panel designs.

From Applied Materials Inc. 15 Apr 2010

American Semiconductor Completes 130nm Flexfet Chip Design

American Semiconductor today announced the first pass success of a 130nm chip design using their proprietary Flexfet technology and Silvaco's Mixed-Signal EDA tool flow. This advanced design, which was developed f...

15 Apr 2010

Intel Updates on Next Generation Core Processors Using 32-nm Microarchitecture

At its developer conference today, Intel Corporation demonstrated how the company is providing a foundation on which to build common hardware, software and ecosystem solutions to make computing experiences and devices work together seamlessly and easier to use.

15 Apr 2010

Azuro Announces Inclusion of its CTS Tool in Second ISF Release in 65nm from TSMC

Azuro, Inc., a leading provider of advanced clock tree synthesis and timing optimization tools for digital chip design, today announced the inclusion of its PowerCentric™ low power clock tree synthesis tool in the second release of TSMC’s Integrated Sign-off Flow (ISF) in 65nm.

From TSMC Taiwan Semiconductor Manufacturing Company 15 Apr 2010