STATS ChipPAC Ltd. ("STATS ChipPAC" or the "Company") (SGX-ST: STATSChP), a leading semiconductor test and advanced packaging service provider, today announced the expansion of its wafer level package (WLP) offering with new 300mm manufacturing capabilities in Taiwan.
The 300mm WLP operation is synergistically located in Hsin-chu Hsien in proximity to the world's leading wafer foundries and supplements the Company's current 300mm wafer bumping operation. The 300mm WLP offering also notably includes a number of new process technologies such as low cure temperature polymers and the use of copper for under bump metallization (UBM) and redistribution layers (RDL) to achieve higher densities and increased package reliability.
Wafer level packages differ from laminate and leadframe based packages in that all of the manufacturing process steps are performed in parallel at the silicon wafer level rather than sequentially on individual semiconductor chips. As a result, a wafer level chip scale package (WLCSP) is essentially the same size as the die, providing a more compact package footprint than conventional manufacturing processes.
"Wafer level packaging has been one of the fastest growing package types in the industry with demand that has outpaced the available market capacity. As a small, lightweight, high performance semiconductor solution, WLCSP is a compelling, cost effective solution for space constrained mobile applications," said Dr. Han Byung Joon, Executive Vice President and Chief Technology Officer, STATS ChipPAC. "The expansion of our 300mm wafer level packaging is important because it provides a significant increase in total available capacity for our customers and allows us to drive higher efficiencies and economy of scale in our wafer level processes for more cost effective packaging solutions."
With wafer level packaging, the cost per package is primarily determined by the number of die per wafer rather than the number of input/output (I/O) per device. STATS ChipPAC has benefited from a successful production ramp up in wafer level packaging and has more than doubled its production volume in Asia since 2009. The expansion to the larger scale 300mm wafers for WLP reinforces STATS ChipPAC's commitment to deliver production capacity and capabilities in strategic locations to service its customers with full turnkey WLCSP assembly and test services for both 200mm and 300mm wafer sizes.
STATS ChipPAC's new process technologies such as electroplated copper RDL and UBM enable customers to achieve higher densities and increased reliability in their wafer level packages. To support a wider range of applications, the Company has completed qualification on WLCSP body sizes up to 5x5mm with qualification underway for 7x7mm.
Han continued, "The new 300mm wafer level packaging capability in Taiwan is one important facet of our broader wafer level packaging portfolio which includes wafer bump, Fan-Out Wafer Level Chip Scale Packaging (eWLB), Integrated Passive Device (IPD) and Through Silicon Via (TSV) technology."