Posted in | Nanoelectronics

IC Knowledge’s Cost Analysis Reveals FD-SOI Process Yields Cost-Economic Wafers

IC Knowledge, a research firm, has conducted a detailed cost analysis that revealed that fully depleted silicon-on-insulator (FD-SOI) wafers provide economic solutions to the semiconductor industry, for manufacturing semiconductor devices based on advanced 22 nm technology node or more.

IC Knowledge joined hands with Soitec and a wafer-processing consultant to conduct the cost - analysis and identified three sampling processes for the 22 nm-based technology node. The three process flows include one planar bulk CMOS and two models of FD-SOI, one processed with implanted drain/source and the other with in-situ doped drain/source. The three process flows involved two gate oxides, three threshold voltages that are suitable for system-on-a-chips (SOCs) applications.

IC Knowledge applied its strategic cost method to validate the performance of each process flow implemented in a Taiwanese wafer fab that produces 30,000 wafers in a month based on 2012 timeframe. The research team measured all the costs such as direct and in-direct labor cost, initial wafers cost, equipment maintenance-cost, wafer fab depreciation-cost, electricity cost, wafer monitoring-cost, and consumables cost that include cost of gases, chemicals, and reticle sets. The cost of a single yielded-wafer was calculated and evaluated by IC Knowledge using gathered information of wafer cost from wafer fabs all over the semiconductor industry.

The analysis carried by strategic cost method revealed that the cost of wafer yielded through FD-SOI model processed with an in-situ doped drain/source was more economical, amounting to $3,000 for a single wafer. In addition, the two versions of FD-SOI were found to be cost-saving than the bulk CMOS process. Their analysis showed that there was only 1% difference in the cost of yielded-wafer between FD-SOI processed with implanted drain/source and the bulk CMOS process.

Source: http://www.icknowledge.com/

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