Semiconductor design and verification solutions provider, Cadence Design Systems has achieved TSMC Phase I 20 nm certification for its Encounter digital and Virtuoso analog design platforms. The certification covers the tools for 20 nm design and implementation and SPICE models for verification and signoff.
As part of the 20 nm design rule, the company’s Encounter digital flow includes novel pattern placement, routing, clocking and optimization of circuit board space. The certification for the Virtuoso analog platform includes its SKILL parameterized cell (Pcell) abutment for complex device design and integrated Physical Verification System (PVS) and Design Rule checking (DRC) for in-design loop detection. The certification for design signoff covers the Encounter Power System for IR and electromigration and Cadence QRC Extraction for physical calculations are included apart from the PVS and DRC. Cadence is currently attempting to achieve TSMC certification for its Encounter Timing System.
Dave Desharnais, Director of Product Marketing of the Silicon Realization Group at Cadence, stated the achievement of the certification was the result of collaborative efforts between Cadence and TSMC and it would facilitate the transition for the semiconductor companies associated with Cadence to 20 nm node.
The company has its headquarters at San Jose, California and has research centers and sales offices in various countries. It provides both software and hardware solutions for design and verification to a host of industries such as semiconductors, networking, telecommunications, computer systems and consumer electronics.
Source: http://www.cadence.com