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Kilopass Anti Fuse OTP eNVM Completes JEDEC Testing for GLOBALFOUNDRIES’ 40nm Low Power Process Technology

Kilopass Technology Inc., a leading provider of logic embedded non-volatile memory (eNVM) intellectual property (IP) and a GLOBALSOLUTIONS Partner, today announced that its entire product line of anti fuse one-time programmable (OTP) eNVM has completed 1000 hours of JEDEC standard reliability testing for GLOBALFOUNDRIES’ 40nm low power process technology.

Kilopass’ eNVM product line offers up to 2Mb of storage capacity and is ready for immediate customer production. Two customers are in final preparation for production on GLOBALFOUNDRIES’ 40nm LP process.

“As 40nm enters mainstream adoption, we work hard with all our IP partners to make sure the ecosystem delivers high-yield, high-quality mass production,” said Dan Weed, director, design solutions at GLOBALFOUNDRIES. “We appreciate Kilopass’ diligence and expertise to complete the rigorous qualification according to JEDEC standard for non-volatile memory.”

Kilopass’ JEDEC qualified antifuse technology makes it an ideal choice for mainstream system-on-chip (SoC) design teams developing SoCs for digital entertainment and consumer electronics at GLOBALFOUNDRIES. Implemented in standard logic CMOS without requiring any additional backend process steps, Kilopass eNVM IP provides up to 2Mb of highly secure storage capacity with 10 years or more of reliable read operation in environmental extremes from -40 to 125°C. Kilopass supports in-system programming without process or mask modifications, thus enabling low manufacturing costs.

“We are pleased to have completed JEDEC qualification on GLOBALFOUNDIRES 40nm LP process just in time to meet the mass production requirements of two of our mutual customers and significant interests from several other Kilopass licensees,” said Kilopass VP of R&D, Harry Luan. “We are impressed with the GLOBALFOUNDRIES advanced process node roadmap and we are continuing our enablement efforts with them to serve our mutual customers.”

About JEDEC 3-Lot Qual

Because semiconductor designs are expected to work in extreme conditions from -40C to 120C (from Alaska in winter to the inside of a car in Phoenix in the summer) for 10 years or more of life, each new SoC design must be tested to ensure it meets this requirement. JEDEC (Joint Electron Device Engineering Council), a developer of open standards for the microelectronics industry, established an accelerated testing methodology to simulate 10 years of operating life in these extreme conditions. It requires representative samples composed of approximately equal numbers from at least three (3) nonconsecutive lots of silicon chips. The lots are tested for correct operation while being subjected to alternating period of extreme heat and cold.

Availability

Kilopass XPM and Gusto NVM IP are currently available for licensing on GLOBALFOUNDRIES 40nm LP process. Contact [email protected] for more information. Kilopass will exhibit at ARM® TechCon 2013 in Booth #806 and demonstrate its OTP eNVM Wednesday and Thursday, October 30-31, at the Santa Clara Convention Center, Santa Clara, Calif.

Source: http://www.kilopass.com/

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