Synopsys' IC Compiler II Receives TSMC Certification for 16nm FinFET Plus Process

Synopsys, Inc. today announced TSMC's certification of the IC Compiler™ II place and route solution on TSMC's 16-nm FinFET Plus (16FF+) process. Synopsys' IC Compiler II is the successor to IC Compiler, the industry's widely adopted place and route solution for advanced designs at both established and emerging nodes.

In addition to the completion of certification in N16 FinFET Plus, Synopsys and TSMC are actively working on IC Compiler II certification in 10 nanometer, underscoring the proven, long-standing partnership and close collaboration on leading-edge technology development between the two companies. Derived from its "rethink, rebuild and reuse" development strategy, IC Compiler II benefits from a range of industry-first technologies that deliver breakthrough capacity and quality of results (QoR).

"N16 FinFET Plus certification marks the first milestone of TSMC and Synopsys collaboration on IC Compiler II," said Bijan Kiani, vice president of product marketing for the Design Group at Synopsys, Inc. "TSMC's rigorous, formal certification opens the door for designers to benefit more broadly from the capacity, throughput and productivity that IC Compiler II offers. We are now actively working on IC Compiler II certification for TSMC 10-nanometer process."

IC Compiler II is a full-featured place and route system architected from the ground-up to realize a substantial leap forward in designer productivity. It is built on a new, multi-threaded infrastructure able to handle large designs while continuing to utilize industry standard input and output formats, as well as familiar interfaces and process technology files. Leveraging this new infrastructure, IC Compiler II offers ultra-high capacity design planning, new clock-building technology and patented global analytical optimization enabling enhanced QoR in area, timing and power. Balancing innovation with strategic reuse of technologies in IC Compiler, IC Compiler II deploys the foundry-proven Zroute router and the linear-gradient placer that together with other innovative IC Compiler II technologies deliver full-flow color enablement, support for connected poly-on-gate oxide and diffusion edge (CPODE) technology, smart layer optimization, low Vdd timing closure and integrated support for signal electro-migration.

"The certification of IC Compiler II on our latest, 16-nanometer production FinFET Plus process brings our industry-leading flows and methodologies to our mutual customers at this exciting production node," said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division. "Our long, ongoing and deep collaboration with Synopsys served as the solid foundation to enable this certification collaboration."

Source: http://www.synopsys.com/

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