Mentor Graphics Corporation (Nasdaq:MENT) today announced that STMicroelectronics has adopted the TestKompress® automatic test pattern generation (ATPG) product into its standard 65nm and 45nm design kits. The new test flow will enable high-quality scan-based production testing for applications such as automotive, cellular infrastructure, and imaging.
“We’re benefiting from a very fruitful collaboration to incorporate Mentor Graphics’ Design-For-Test (DFT) technology into our advanced nanometer design flows starting at 65nm and below,” said Roberto Mattiuzzo, Digital Test Solutions manager of STMicroelectronics’ Technology R&D, Central CAD & Design Solutions. “With new failure mechanisms at advanced nodes, limitations on IC pins available for testing, and the need to employ better self-test in the field, the range of emerging testing requirements has significantly increased. We are therefore pleased to add Mentor Graphics in the portfolio of EDA solutions supported by STMicroelectronics in the Design-For-Test area.”
The move to smaller geometries introduces new subtle failure mechanisms that can be missed by relying solely on traditional scan testing using only static fault models. Applications that demand the highest quality devices require additional test patterns that specifically target these new failure mechanisms. STMicroelectronics employs a variety of manufacturing tests including timing-aware at-speed tests and layout-aware bridging tests to ensure the quality of their semiconductor products. Mentor’s TestKompress compression technology allows these additional tests to be added while at the same time reducing test data volume and test time. STMicroelectronics is also using Mentor DFT tools to add in-system testing to its high-reliability products to enable a fast check of system integrity and simplified trouble-shooting in the field.
“We have taped out a 65nm design with production testing employing Mentor’s TestKompress product, which enabled us to meet our rigid target in terms of test coverage,” said Angelo Oldani, Design Group Director in Communication Infrastructure Division of Computer and Communication Infrastructure product group, STMicroelectronics. “Mentor’s strong cooperation and support also helped us to use the LBISTArchitect product to add logic built-in self test (LBIST), allowing device testing in the real application to ensure reliable operation in demanding end-product applications.”
The high compression capabilities of TestKompress can also be used to implement a low-pin count testing strategy, enabling high-quality tests to be applied to a wide variety of components including system in package (SiP) devices with limited pads for testing. Low pin count testing can also be used to enable multi-site testing to increase test throughput. “We’re using the high compression advantages of TestKompress to meet our need for very low pin count testing on our imaging ICs,” said Jocelyn Moreau, DFT Manager in the Imaging Division, Home Entertainment & Displays group, STMicroelectronics. “We were able to achieve our test coverage and quality goals with as few as three digital pins available on these devices. This approach is accelerating the adoption of high compression scan testing for future designs.”
Mentor’s DFT product line, the market share leader in digital IC testing, provides a complete solution for advanced digital IC production testing, including scan-based test and BIST logic insertion, ATPG, test pattern debugging, and test failure diagnosis. Mentor’s award-winning and patented Embedded Deterministic Test (EDT) technology provides the highest test pattern compression available, addressing the critical requirements of advanced SoC nano-scale designs. Mentor’s DFT product line is also the market share leader in digital ATPG.