Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, and NEC Electronics Corporation (TSE: 6723), a leading provider of semiconductor solutions, today announced that NEC Electronics has adopted Cadence® Encounter® Digital Implementation (EDI) System and succeeded in more than ten complex ASIC designs targeting its CB40L (40 nanometer low power) process technology with several designs successfully taped out already.
Utilizing more than 20 million gates, the scale of the new ASICs has increased by two- to four-times over previous designs targeting 55-nanometer (nm) and 90-nm process technologies. EDI Systems' multi-threaded processing, netlist-to-netlist compilation, and integrated DFM optimization and timing signoff analysis, streamlined the large ASIC design processes.
"We are quite satisfied that the Cadence EDI System is fully capable of tackling our leading edge design challenges," said Akira Denda, Department Manager of the Device Platform Development Department, 1st SoC Business Planning Division at NEC Electronics ASIC Division. "EDI System enabled us to tapeout an area-efficient design while sustaining time-to-market by leveraging the end-to-end, multi-threaded solution."
The Cadence EDI System is a configurable and extensible high performance, high capacity, scalable design solution for high-density electronic design.
The larger an ASIC design becomes, the more variables stand in the way of correct implementation. EDI System and its key components, including Encounter Timing System and Encounter RTL Compiler, combine to bring predictability back into the equation, resulting in higher-quality silicon. At the same time, the multiprocessing capability of the integrated system enabled over 20 million-gate designs to be delivered with little increase in turnaround time. In addition, engineers can realize significant power savings and yield enhancement through advanced low power design and optimization techniques.
EDI System also provides a complete, consistent, and converging flow to address design-for-manufacturing (DFM) and variability effects (lithography, CMP, thermal, and process variations) in the early stages of the design flow. By integrating model-based DFM and statistical technology in a comprehensive prevention-analysis-repair flow, the Cadence solution is capable of handling huge designs and provides significant productivity gains over traditional DFM-closure solutions.
"The Cadence EDI System provides significantly improved productivity and time-to-market, while reducing both the cost and risk associated with advanced semiconductor design," said Dr. Chi-Ping Hsu, senior vice president of implementation research and development at Cadence. "The EDI System enabled NEC Electronics to tape-out its 40-nm ASIC designs, involving the incredibly complex integration of over 20 million gates in a single, low-power, area-efficient device. We're already lined up to execute additional advanced node designs with NEC Electronics, using EDI System with advanced node capabilities to reach fast, predictable design convergence."