STMicroelectronics Utilizes IC Compiler II to Tape Out Complex 28nm-FD-SOI SoC

Synopsys, Inc. today announced STMicroelectronics, a global semiconductor leader serving customers across the spectrum of electronics applications, has taped out their latest fully depleted silicon on insulator (FD-SOI) system on chip (SoC) using Synopsys' IC Compiler™ II place and route solution.

Collaborating closely with Synopsys, ST used the tool to complete more than half of the chip, achieving higher designer productivity and better device performance. Unveiled in 2014, IC Compiler II is the successor to IC Compiler, the industry's current leading place and route solution for advanced design at established and emerging nodes. Driven by the FD-SOI tapeout success, ST is actively engaged in broadening the usage of IC Compiler II.

"Looking back, we can safely say it would have been exceedingly difficult to do a chip of this magnitude without IC Compiler II," said Thierry Bauchon, R&D Director at STMicroelectronics. "Our experience proved the promise we saw early in the design with 10X faster design exploration and 5X faster implementation, enabling us to refine floorplans, up-size physical partitions and achieve faster clock speeds on this tapeout."

IC Compiler II is a production-ready, full-featured place and route system architected from the ground-up to realize an order-of-magnitude leap forward in designer productivity. It is built on a new multi-threaded infrastructure able to handle designs with more than 500 million instances while continuing to utilize industry-standard input and output formats, as well as familiar interfaces and process technology files. Leveraging this new infrastructure, IC Compiler II offers ultra-high-capacity design planning, unique new clock-building technology and patented global analytical optimization, enabling enhanced quality of results (QoR) in area, timing and power. Representing years of engineering innovation and featuring several dozen new patents, these innovative technologies enable IC Compiler II to deliver 5X faster runtime along with half the memory and half the iterations required to achieve target QoR – all together enabling a 10X boost in design throughput. This level of speed-up is already enabling game-changing possibilities for IC Compiler II users and is continuing to transform how physical design is done.

"Over the years ST has been a steadfast partner helping us develop and deploy advanced design technology, and that has continued with our very latest offering, IC Compiler II," said Antun Domic, executive vice president and general manager of the Design Group at Synopsys.  "The successful tapeout underscores the unique value IC Compiler II is delivering to a rapidly growing user base."

Source: http://www.synopsys.com

Citations

Please use one of the following formats to cite this article in your essay, paper or report:

  • APA

    Synopsys, Inc.. (2019, February 11). STMicroelectronics Utilizes IC Compiler II to Tape Out Complex 28nm-FD-SOI SoC. AZoNano. Retrieved on October 06, 2022 from https://www.azonano.com/news.aspx?newsID=32911.

  • MLA

    Synopsys, Inc.. "STMicroelectronics Utilizes IC Compiler II to Tape Out Complex 28nm-FD-SOI SoC". AZoNano. 06 October 2022. <https://www.azonano.com/news.aspx?newsID=32911>.

  • Chicago

    Synopsys, Inc.. "STMicroelectronics Utilizes IC Compiler II to Tape Out Complex 28nm-FD-SOI SoC". AZoNano. https://www.azonano.com/news.aspx?newsID=32911. (accessed October 06, 2022).

  • Harvard

    Synopsys, Inc.. 2019. STMicroelectronics Utilizes IC Compiler II to Tape Out Complex 28nm-FD-SOI SoC. AZoNano, viewed 06 October 2022, https://www.azonano.com/news.aspx?newsID=32911.

Tell Us What You Think

Do you have a review, update or anything you would like to add to this news story?

Leave your feedback
Your comment type
Submit