CEA-LETI Extends Transistor Dimension Scaling Using 3D Nanowire FET

CEA-LETI has successfully integrated on the same SOI wafer different types of advanced transistor structures like stacked nanowires transistors, FINFETs and independent dual gate FET, using a common flow compatible with standard planar FDSOI devices.

This achievement open the way to adopting different device structures in the same chip to optimise performance, density and power consumption. The devices were processed within CEA-LETI facilities where the e-beam lithography platform allowed the fabrication of 15nm gate length devices.

The work was carried out in the frame of the French Carnot Institutes initiative and in collaboration with the IMEP Grenoble and STMicroelectronics Crolles. The full results showing the structures and the electrical results will be presented at IEDM conference next December where CEA-LETI will participate with over 10 papers on different aspects of nanotechnologies, advanced devices and process integration.

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