Feb 3 2009
Virage Logic (NASDAQ: VIRL), the semiconductor industry's trusted IP partner, today announced that Sharp Corporation, the industry leader in CMOS image sensor (CIS) applications targeting high-end cell phone designs, has selected Virage Logic's Area, Speed and Power (ASAP) Memory IP architecture to be optimized for its latest CMOS image sensor devices. This agreement expands Sharp Corporation's long-standing collaboration with Virage Logic and underscores Virage Logic's leadership position as a cost-effective source for IP used in performance-intensive small form-factor products. Virage Logic's ASAP High-Density embedded memory architectures will be implemented on Sharp's next-generation CIS process.
“Our sensor modules lead the market for their compactness, and we must continue to meet market needs by incorporating high performance features into compact, cost-effective designs,” said a management spokesperson for Sharp Corporation's Imaging and Sensing Module Division. “We knew we could rely on Virage Logic as our trusted IP partner because of their expertise in the CIS market, and their long track record in providing application optimized, silicon proven IP.”
“As small form factor devices become increasingly sophisticated, more functionality must be designed into the system-on-chip (SoC) in order to remain competitive and meet the requirements of today's on-the-go lifestyle,” said Brani Buric, executive vice president of marketing, Virage Logic. “We are pleased that our highly differentiated IP is able to help a market leader such as Sharp cost effectively meet their customers' requirements for camera-capable handheld devices like cell phones.”
Virage Logic offers a broad embedded memory product portfolio. The ASAP Memory product line provides the largest selection of embedded memories and includes High-Density compilers optimized for area, High-Speed compilers optimized for speed-critical applications, and Ultra-Low-Power memory compilers optimized for battery-powered and hand-held applications. The company's SiWare™ Memory product line of silicon aware compilers provides the world's most power-optimized memories for advanced processes at 65nm and 40nm. These high performance memory compilers minimize both static and dynamic power consumption and provide optimal yields. SiWare High-Density memory compilers are optimized to generate memories with the absolute minimum area while SiWare High-Speed memory compilers are designed to help designers achieve the most aggressive critical path requirements. The company's STAR™ Memory product line provides embedded memories designed for testability and manufacturability to optimize yield. Building on the ASAP Memory product line, STAR memories include redundancy capabilities for repair purposes.