Posted in | Nanoelectronics

STMicroelectronics Selects Cadence QRC Extraction for 40nm Technology Design

Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that STMicroelectronics, a global leader in integrated circuits for communications, consumer, computer, automotive and industrial applications, has standardized on Cadence® QRC Extraction for their 40-nanometer custom/analog designs.

A key component of the Cadence digital and analog/mixed signal design flow, QRC Extraction enables faster turnaround time, scalability through its multi-core backplane, increased accuracy to silicon and capabilities to address the needs for advanced layout parasitic extraction in leading-edge technology node design.

As process geometries continue to shrink beyond 40nm, it becomes imperative for parasitic extraction to understand and accurately model and predict the impact of substrate, inductance and mutual inductance on the performance of a chip. Cadence QRC Extraction constantly breaks new ground and is the first to be certified at advanced nodes by leading foundries. Along with feature-rich advancements in leading-edge process modeling and integration with the Virtuoso Custom® IC and Encounter® Digital Implementation Platforms, QRC is the tool that provides a seamless single parasitic solution for digital, custom, RF, memory, analog, mixed-signal and substrate extraction. STMicroelectronics' customers and design centers easily realized the differentiated productivity and silicon predictability benefits.

"We evaluated Cadence QRC Extraction and found it competitive to be included in our 40LP analog/RF mixed-signal/digital signoff design flow. Our customers and designers are bound to benefit from its adoption in terms of higher design performance," said Vincent Varo, CMOS and Derivative PDK Manager, Technology R&D, STMicroelectronics. "Our evaluation confirmed that QRC Extraction is able to manage the complexity of advanced 40nm effects with suitable model accuracy, besides its seamless integration with the Cadence Virtuoso and Encounter design environments."

To qualify for the ST extraction flow, QRC Extraction passed a rigorous evaluation involving multiple designs and dozens of criteria. With the successful conclusion of this evaluation, QRC Extraction technology was qualified to be a part of the 40LP methodology widely deployed to ST's design centers developing large-scale, complex digital and analog designs.

"We are pleased that the Cadence QRC signoff solution continues to gain critical acclaim for providing differentiated results for STMicroelectronics, which is one of the world's most sophisticated leaders in driving CAD-solutions for broad range of analog and mixed-signal IC products in various domain like wireless, Wifi, Bluetooth in 40nm Low-power Technology Design Platform with vast experience in PDK and custom layout methodology," said Dr. Rachid Salik, vice president of research and development at Cadence. "It is our passion to work together with leading companies, such as STMicroelectronics."



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