Cadence Design Systems, Inc. today announced that its Cadence® Innovus™ Implementation System has achieved V0.9 certification for TSMC’s 10nm FinFET process and is currently on track to complete V1.0 in Q4 2015.
The Innovus Implementation System is a next-generation physical implementation tool that incorporates integrated signoff engines that have been validated by TSMC on high-performance reference designs, providing customers with a fast path to implementation, closure, and optimal power, performance and area (PPA).
The Innovus Implementation System offers customers key technologies needed to stay in front of the competition using the TSMC 10nm process. Some of the technology capabilities include:
- GigaPlace™ solver-based placement technology – The pin-access-aware feature ensures the cells are placed in accordance with 10nm orientation, coloring and edge-constraint requirements to avoid downstream routing issues, while enabling designers to meet aggressive timing and area metrics
- Embedded accurate extraction, delay calculation and power calculation engines – Integration with signoff tools—Quantus™ QRC Extraction Solution, Tempus™ Timing Signoff Solution, Voltus™ IC Power Integrity Solution and Physical Verification System—ensures that there are consistent results across the different steps of the 10nm implementation flow, which improves design closure and signoff schedule predictability
- Global optimization engines – Provides optimal performance and power during implementation while taking 10nm process variation into account
- Massively parallel architecture – Increases capacity and drives better turnaround times without compromising the quality of results (QoR), despite the tight constraints imposed by 10nm technology geometries
For more information on the Innovus Implementation System, please visit www.cadence.com/news/innovus.
“The Innovus Implementation System allows customers to achieve TSMC’s 10nm FinFET process benefits of smaller area, higher performance and lower power consumption with a reduced turnaround time,” said Dr. Anirudh Devgan, senior vice president and general manager of the Digital and Signoff Group at Cadence. “Our continued collaboration with TSMC on the Innovus Implementation System certification provides customers with confidence that they can attain consistent results and meet aggressive schedules.”
“We worked closely with Cadence to certify the Innovus Implementation System to meet TSMC’s 10nm FinFET requirements,” said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division. “Through the certification collaboration, we provide design solutions for our joint customers to deliver innovative, advanced-node designs to market.”
In related news, please see the Cadence press release titled, “Cadence Digital, Custom/Analog and Signoff Tools Achieve TSMC Certification for 10nm FinFET Process,” at http://www.cadence.com/cadence/newsroom/press_releases/Pages/pr.aspx?xml=091615_tsmc10nmFFcert.